287 lines
8.1 KiB
C
287 lines
8.1 KiB
C
#ifndef __SPARC_SYSTEM_H
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#define __SPARC_SYSTEM_H
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#include <linux/kernel.h>
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#include <linux/threads.h> /* NR_CPUS */
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#include <linux/thread_info.h>
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#include <asm/page.h>
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#include <asm/psr.h>
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#include <asm/ptrace.h>
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#include <asm/btfixup.h>
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#include <asm/smp.h>
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#ifndef __ASSEMBLY__
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#include <linux/irqflags.h>
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/*
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* Sparc (general) CPU types
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*/
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enum sparc_cpu {
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sun4 = 0x00,
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sun4c = 0x01,
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sun4m = 0x02,
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sun4d = 0x03,
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sun4e = 0x04,
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sun4u = 0x05, /* V8 ploos ploos */
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sun_unknown = 0x06,
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ap1000 = 0x07, /* almost a sun4m */
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};
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/* Really, userland should not be looking at any of this... */
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#ifdef __KERNEL__
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extern enum sparc_cpu sparc_cpu_model;
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#ifndef CONFIG_SUN4
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#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
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#define ARCH_SUN4 0
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#else
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#define ARCH_SUN4C_SUN4 1
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#define ARCH_SUN4 1
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#endif
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#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
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extern char reboot_command[];
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extern struct thread_info *current_set[NR_CPUS];
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extern unsigned long empty_bad_page;
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extern unsigned long empty_bad_page_table;
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extern unsigned long empty_zero_page;
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extern void sun_do_break(void);
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extern int serial_console;
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extern int stop_a_enabled;
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static inline int con_is_present(void)
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{
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return serial_console ? 0 : 1;
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}
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/* When a context switch happens we must flush all user windows so that
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* the windows of the current process are flushed onto its stack. This
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* way the windows are all clean for the next process and the stack
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* frames are up to date.
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*/
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extern void flush_user_windows(void);
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extern void kill_user_windows(void);
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extern void synchronize_user_stack(void);
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extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
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void *fpqueue, unsigned long *fpqdepth);
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#ifdef CONFIG_SMP
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#define SWITCH_ENTER(prv) \
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do { \
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if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
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put_psr(get_psr() | PSR_EF); \
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fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
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&(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
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clear_tsk_thread_flag(prv, TIF_USEDFPU); \
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(prv)->thread.kregs->psr &= ~PSR_EF; \
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} \
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} while(0)
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#define SWITCH_DO_LAZY_FPU(next) /* */
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#else
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#define SWITCH_ENTER(prv) /* */
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#define SWITCH_DO_LAZY_FPU(nxt) \
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do { \
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if (last_task_used_math != (nxt)) \
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(nxt)->thread.kregs->psr&=~PSR_EF; \
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} while(0)
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#endif
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/*
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* Flush windows so that the VM switch which follows
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* would not pull the stack from under us.
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*
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* SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
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* XXX WTF is the above comment? Found in late teen 2.4.x.
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*/
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#define prepare_arch_switch(next) do { \
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__asm__ __volatile__( \
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".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
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"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
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"save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
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"save %sp, -0x40, %sp\n\t" \
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"restore; restore; restore; restore; restore; restore; restore"); \
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} while(0)
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/* Much care has gone into this code, do not touch it.
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*
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* We need to loadup regs l0/l1 for the newly forked child
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* case because the trap return path relies on those registers
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* holding certain values, gcc is told that they are clobbered.
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* Gcc needs registers for 3 values in and 1 value out, so we
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* clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
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*
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* Hey Dave, that do not touch sign is too much of an incentive
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* - Anton & Pete
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*/
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#define switch_to(prev, next, last) do { \
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SWITCH_ENTER(prev); \
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SWITCH_DO_LAZY_FPU(next); \
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cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
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__asm__ __volatile__( \
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"sethi %%hi(here - 0x8), %%o7\n\t" \
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"mov %%g6, %%g3\n\t" \
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"or %%o7, %%lo(here - 0x8), %%o7\n\t" \
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"rd %%psr, %%g4\n\t" \
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"std %%sp, [%%g6 + %4]\n\t" \
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"rd %%wim, %%g5\n\t" \
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"wr %%g4, 0x20, %%psr\n\t" \
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"nop\n\t" \
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"std %%g4, [%%g6 + %3]\n\t" \
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"ldd [%2 + %3], %%g4\n\t" \
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"mov %2, %%g6\n\t" \
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".globl patchme_store_new_current\n" \
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"patchme_store_new_current:\n\t" \
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"st %2, [%1]\n\t" \
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"wr %%g4, 0x20, %%psr\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
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"ldd [%%g6 + %4], %%sp\n\t" \
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"wr %%g5, 0x0, %%wim\n\t" \
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"ldd [%%sp + 0x00], %%l0\n\t" \
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"ldd [%%sp + 0x38], %%i6\n\t" \
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"wr %%g4, 0x0, %%psr\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"jmpl %%o7 + 0x8, %%g0\n\t" \
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" ld [%%g3 + %5], %0\n\t" \
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"here:\n" \
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: "=&r" (last) \
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: "r" (&(current_set[hard_smp_processor_id()])), \
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"r" (task_thread_info(next)), \
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"i" (TI_KPSR), \
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"i" (TI_KSP), \
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"i" (TI_TASK) \
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: "g1", "g2", "g3", "g4", "g5", "g7", \
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"l0", "l1", "l3", "l4", "l5", "l6", "l7", \
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"i0", "i1", "i2", "i3", "i4", "i5", \
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"o0", "o1", "o2", "o3", "o7"); \
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} while(0)
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/* XXX Change this if we ever use a PSO mode kernel. */
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define read_barrier_depends() do { } while(0)
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#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
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#define smp_mb() __asm__ __volatile__("":::"memory")
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#define smp_rmb() __asm__ __volatile__("":::"memory")
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#define smp_wmb() __asm__ __volatile__("":::"memory")
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#define smp_read_barrier_depends() do { } while(0)
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#define nop() __asm__ __volatile__ ("nop")
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/* This has special calling conventions */
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#ifndef CONFIG_SMP
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BTFIXUPDEF_CALL(void, ___xchg32, void)
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#endif
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static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
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{
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#ifdef CONFIG_SMP
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__asm__ __volatile__("swap [%2], %0"
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: "=&r" (val)
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: "0" (val), "r" (m)
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: "memory");
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return val;
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#else
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register unsigned long *ptr asm("g1");
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register unsigned long ret asm("g2");
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ptr = (unsigned long *) m;
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ret = val;
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/* Note: this is magic and the nop there is
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really needed. */
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___f____xchg32\n\t"
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" nop\n\t"
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: "=&r" (ret)
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: "0" (ret), "r" (ptr)
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: "g3", "g4", "g7", "memory", "cc");
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return ret;
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#endif
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
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{
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switch (size) {
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case 4:
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return xchg_u32(ptr, x);
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};
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__xchg_called_with_bad_pointer();
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return x;
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}
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/* Emulate cmpxchg() the same way we emulate atomics,
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* by hashing the object address and indexing into an array
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* of spinlocks to get a bit of performance...
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*
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* See arch/sparc/lib/atomic32.c for implementation.
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*
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* Cribbed from <asm-parisc/atomic.h>
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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/* bug catcher for when unsupported size is used - won't link */
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extern void __cmpxchg_called_with_bad_pointer(void);
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/* we only need to support cmpxchg of a u32 on sparc */
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extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
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/* don't worry...optimizer will get rid of most of this */
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
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default:
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__cmpxchg_called_with_bad_pointer();
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break;
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}
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#include <asm-generic/cmpxchg-local.h>
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#define arch_align_stack(x) (x)
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#endif /* !(__SPARC_SYSTEM_H) */
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