1098 lines
28 KiB
C
1098 lines
28 KiB
C
/*
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* NCR53c406.c
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* Low-level SCSI driver for NCR53c406a chip.
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* Copyright (C) 1994, 1995, 1996 Normunds Saumanis (normunds@fi.ibm.com)
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*
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* LILO command line usage: ncr53c406a=<PORTBASE>[,<IRQ>[,<FASTPIO>]]
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* Specify IRQ = 0 for non-interrupt driven mode.
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* FASTPIO = 1 for fast pio mode, 0 for slow mode.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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*/
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#define NCR53C406A_DEBUG 0
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#define VERBOSE_NCR53C406A_DEBUG 0
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/* Set this to 1 for PIO mode (recommended) or to 0 for DMA mode */
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#define USE_PIO 1
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#define USE_BIOS 0
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/* #define BIOS_ADDR 0xD8000 *//* define this if autoprobe fails */
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/* #define PORT_BASE 0x330 *//* define this if autoprobe fails */
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/* #define IRQ_LEV 0 *//* define this if autoprobe fails */
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#define DMA_CHAN 5 /* this is ignored if DMA is disabled */
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/* Set this to 0 if you encounter kernel lockups while transferring
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* data in PIO mode */
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#define USE_FAST_PIO 1
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/* ============= End of user configurable parameters ============= */
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/proc_fs.h>
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#include <linux/stat.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <linux/blkdev.h>
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#include <linux/spinlock.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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/* ============================================================= */
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#define WATCHDOG 5000000
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#define SYNC_MODE 0 /* Synchronous transfer mode */
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#ifdef DEBUG
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#undef NCR53C406A_DEBUG
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#define NCR53C406A_DEBUG 1
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#endif
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#if USE_PIO
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#define USE_DMA 0
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#else
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#define USE_DMA 1
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#endif
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/* Default configuration */
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#define C1_IMG 0x07 /* ID=7 */
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#define C2_IMG 0x48 /* FE SCSI2 */
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#if USE_DMA
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#define C3_IMG 0x21 /* CDB TE */
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#else
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#define C3_IMG 0x20 /* CDB */
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#endif
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#define C4_IMG 0x04 /* ANE */
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#define C5_IMG 0xb6 /* AA PI SIE POL */
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#define REG0 (outb(C4_IMG, CONFIG4))
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#define REG1 (outb(C5_IMG, CONFIG5))
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#if NCR53C406A_DEBUG
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#define DEB(x) x
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#else
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#define DEB(x)
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#endif
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#if VERBOSE_NCR53C406A_DEBUG
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#define VDEB(x) x
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#else
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#define VDEB(x)
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#endif
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#define LOAD_DMA_COUNT(count) \
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outb(count & 0xff, TC_LSB); \
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outb((count >> 8) & 0xff, TC_MSB); \
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outb((count >> 16) & 0xff, TC_HIGH);
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/* Chip commands */
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#define DMA_OP 0x80
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#define SCSI_NOP 0x00
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#define FLUSH_FIFO 0x01
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#define CHIP_RESET 0x02
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#define SCSI_RESET 0x03
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#define RESELECT 0x40
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#define SELECT_NO_ATN 0x41
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#define SELECT_ATN 0x42
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#define SELECT_ATN_STOP 0x43
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#define ENABLE_SEL 0x44
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#define DISABLE_SEL 0x45
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#define SELECT_ATN3 0x46
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#define RESELECT3 0x47
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#define TRANSFER_INFO 0x10
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#define INIT_CMD_COMPLETE 0x11
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#define MSG_ACCEPT 0x12
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#define TRANSFER_PAD 0x18
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#define SET_ATN 0x1a
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#define RESET_ATN 0x1b
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#define SEND_MSG 0x20
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#define SEND_STATUS 0x21
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#define SEND_DATA 0x22
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#define DISCONN_SEQ 0x23
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#define TERMINATE_SEQ 0x24
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#define TARG_CMD_COMPLETE 0x25
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#define DISCONN 0x27
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#define RECV_MSG 0x28
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#define RECV_CMD 0x29
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#define RECV_DATA 0x2a
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#define RECV_CMD_SEQ 0x2b
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#define TARGET_ABORT_DMA 0x04
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/*----------------------------------------------------------------*/
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/* the following will set the monitor border color (useful to find
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where something crashed or gets stuck at */
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/* 1 = blue
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2 = green
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3 = cyan
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4 = red
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5 = magenta
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6 = yellow
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7 = white
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*/
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#if NCR53C406A_DEBUG
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#define rtrc(i) {inb(0x3da);outb(0x31,0x3c0);outb((i),0x3c0);}
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#else
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#define rtrc(i) {}
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#endif
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/*----------------------------------------------------------------*/
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enum Phase {
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idle,
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data_out,
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data_in,
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command_ph,
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status_ph,
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message_out,
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message_in
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};
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/* Static function prototypes */
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static void NCR53c406a_intr(int, void *, struct pt_regs *);
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static irqreturn_t do_NCR53c406a_intr(int, void *, struct pt_regs *);
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static void chip_init(void);
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static void calc_port_addr(void);
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#ifndef IRQ_LEV
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static int irq_probe(void);
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#endif
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/* ================================================================= */
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#if USE_BIOS
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static void *bios_base;
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#endif
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#ifdef PORT_BASE
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static int port_base = PORT_BASE;
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#else
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static int port_base;
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#endif
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#ifdef IRQ_LEV
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static int irq_level = IRQ_LEV;
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#else
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static int irq_level = -1; /* 0 is 'no irq', so use -1 for 'uninitialized' */
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#endif
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#if USE_DMA
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static int dma_chan;
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#endif
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#if USE_PIO
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static int fast_pio = USE_FAST_PIO;
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#endif
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static Scsi_Cmnd *current_SC;
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static char info_msg[256];
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/* ================================================================= */
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/* possible BIOS locations */
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#if USE_BIOS
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static void *addresses[] = {
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(void *) 0xd8000,
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(void *) 0xc8000
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};
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#define ADDRESS_COUNT (sizeof( addresses ) / sizeof( unsigned ))
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#endif /* USE_BIOS */
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/* possible i/o port addresses */
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static unsigned short ports[] = { 0x230, 0x330, 0x280, 0x290, 0x330, 0x340, 0x300, 0x310, 0x348, 0x350 };
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#define PORT_COUNT (sizeof( ports ) / sizeof( unsigned short ))
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/* possible interrupt channels */
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static unsigned short intrs[] = { 10, 11, 12, 15 };
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#define INTR_COUNT (sizeof( intrs ) / sizeof( unsigned short ))
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/* signatures for NCR 53c406a based controllers */
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#if USE_BIOS
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struct signature {
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char *signature;
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int sig_offset;
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int sig_length;
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} signatures[] __initdata = {
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/* 1 2 3 4 5 6 */
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/* 123456789012345678901234567890123456789012345678901234567890 */
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{
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"Copyright (C) Acculogic, Inc.\r\n2.8M Diskette Extension Bios ver 4.04.03 03/01/1993", 61, 82},};
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#define SIGNATURE_COUNT (sizeof( signatures ) / sizeof( struct signature ))
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#endif /* USE_BIOS */
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/* ============================================================ */
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/* Control Register Set 0 */
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static int TC_LSB; /* transfer counter lsb */
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static int TC_MSB; /* transfer counter msb */
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static int SCSI_FIFO; /* scsi fifo register */
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static int CMD_REG; /* command register */
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static int STAT_REG; /* status register */
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static int DEST_ID; /* selection/reselection bus id */
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static int INT_REG; /* interrupt status register */
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static int SRTIMOUT; /* select/reselect timeout reg */
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static int SEQ_REG; /* sequence step register */
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static int SYNCPRD; /* synchronous transfer period */
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static int FIFO_FLAGS; /* indicates # of bytes in fifo */
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static int SYNCOFF; /* synchronous offset register */
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static int CONFIG1; /* configuration register */
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static int CLKCONV; /* clock conversion reg */
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/*static int TESTREG;*//* test mode register */
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static int CONFIG2; /* Configuration 2 Register */
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static int CONFIG3; /* Configuration 3 Register */
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static int CONFIG4; /* Configuration 4 Register */
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static int TC_HIGH; /* Transfer Counter High */
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/*static int FIFO_BOTTOM;*//* Reserve FIFO byte register */
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/* Control Register Set 1 */
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/*static int JUMPER_SENSE;*//* Jumper sense port reg (r/w) */
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/*static int SRAM_PTR;*//* SRAM address pointer reg (r/w) */
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/*static int SRAM_DATA;*//* SRAM data register (r/w) */
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static int PIO_FIFO; /* PIO FIFO registers (r/w) */
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/*static int PIO_FIFO1;*//* */
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/*static int PIO_FIFO2;*//* */
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/*static int PIO_FIFO3;*//* */
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static int PIO_STATUS; /* PIO status (r/w) */
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/*static int ATA_CMD;*//* ATA command/status reg (r/w) */
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/*static int ATA_ERR;*//* ATA features/error register (r/w) */
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static int PIO_FLAG; /* PIO flag interrupt enable (r/w) */
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static int CONFIG5; /* Configuration 5 register (r/w) */
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/*static int SIGNATURE;*//* Signature Register (r) */
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/*static int CONFIG6;*//* Configuration 6 register (r) */
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/* ============================================================== */
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#if USE_DMA
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static __inline__ int NCR53c406a_dma_setup(unsigned char *ptr, unsigned int count, unsigned char mode)
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{
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unsigned limit;
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unsigned long flags = 0;
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VDEB(printk("dma: before count=%d ", count));
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if (dma_chan <= 3) {
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if (count > 65536)
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count = 65536;
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limit = 65536 - (((unsigned) ptr) & 0xFFFF);
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} else {
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if (count > (65536 << 1))
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count = (65536 << 1);
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limit = (65536 << 1) - (((unsigned) ptr) & 0x1FFFF);
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}
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if (count > limit)
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count = limit;
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VDEB(printk("after count=%d\n", count));
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if ((count & 1) || (((unsigned) ptr) & 1))
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panic("NCR53c406a: attempted unaligned DMA transfer\n");
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flags = claim_dma_lock();
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disable_dma(dma_chan);
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clear_dma_ff(dma_chan);
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set_dma_addr(dma_chan, (long) ptr);
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set_dma_count(dma_chan, count);
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set_dma_mode(dma_chan, mode);
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enable_dma(dma_chan);
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release_dma_lock(flags);
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return count;
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}
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static __inline__ int NCR53c406a_dma_write(unsigned char *src, unsigned int count)
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{
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return NCR53c406a_dma_setup(src, count, DMA_MODE_WRITE);
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}
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static __inline__ int NCR53c406a_dma_read(unsigned char *src, unsigned int count)
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{
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return NCR53c406a_dma_setup(src, count, DMA_MODE_READ);
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}
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static __inline__ int NCR53c406a_dma_residual(void)
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{
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register int tmp;
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unsigned long flags;
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flags = claim_dma_lock();
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clear_dma_ff(dma_chan);
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tmp = get_dma_residue(dma_chan);
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release_dma_lock(flags);
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return tmp;
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}
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#endif /* USE_DMA */
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#if USE_PIO
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static __inline__ int NCR53c406a_pio_read(unsigned char *request, unsigned int reqlen)
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{
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int i;
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int len; /* current scsi fifo size */
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REG1;
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while (reqlen) {
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i = inb(PIO_STATUS);
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/* VDEB(printk("pio_status=%x\n", i)); */
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if (i & 0x80)
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return 0;
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switch (i & 0x1e) {
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default:
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case 0x10:
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len = 0;
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break;
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case 0x0:
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len = 1;
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break;
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case 0x8:
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len = 42;
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break;
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case 0xc:
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len = 84;
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break;
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case 0xe:
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len = 128;
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break;
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}
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if ((i & 0x40) && len == 0) { /* fifo empty and interrupt occurred */
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return 0;
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}
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if (len) {
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if (len > reqlen)
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len = reqlen;
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if (fast_pio && len > 3) {
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insl(PIO_FIFO, request, len >> 2);
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request += len & 0xfc;
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reqlen -= len & 0xfc;
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} else {
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while (len--) {
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*request++ = inb(PIO_FIFO);
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reqlen--;
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}
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}
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}
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}
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return 0;
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}
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static __inline__ int NCR53c406a_pio_write(unsigned char *request, unsigned int reqlen)
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{
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int i = 0;
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int len; /* current scsi fifo size */
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REG1;
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while (reqlen && !(i & 0x40)) {
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i = inb(PIO_STATUS);
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/* VDEB(printk("pio_status=%x\n", i)); */
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if (i & 0x80) /* error */
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return 0;
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switch (i & 0x1e) {
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case 0x10:
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len = 128;
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break;
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case 0x0:
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len = 84;
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break;
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case 0x8:
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len = 42;
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break;
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case 0xc:
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len = 1;
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break;
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default:
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case 0xe:
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len = 0;
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break;
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}
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if (len) {
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if (len > reqlen)
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len = reqlen;
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if (fast_pio && len > 3) {
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outsl(PIO_FIFO, request, len >> 2);
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request += len & 0xfc;
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reqlen -= len & 0xfc;
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} else {
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while (len--) {
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outb(*request++, PIO_FIFO);
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reqlen--;
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}
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}
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}
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}
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return 0;
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}
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#endif /* USE_PIO */
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static int __init NCR53c406a_detect(struct scsi_host_template * tpnt)
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{
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int present = 0;
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struct Scsi_Host *shpnt = NULL;
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#ifndef PORT_BASE
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int i;
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#endif
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#if USE_BIOS
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int ii, jj;
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bios_base = 0;
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/* look for a valid signature */
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for (ii = 0; ii < ADDRESS_COUNT && !bios_base; ii++)
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for (jj = 0; (jj < SIGNATURE_COUNT) && !bios_base; jj++)
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if (!memcmp((void *) addresses[ii] + signatures[jj].sig_offset, (void *) signatures[jj].signature, (int) signatures[jj].sig_length))
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bios_base = addresses[ii];
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if (!bios_base) {
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printk("NCR53c406a: BIOS signature not found\n");
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return 0;
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}
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DEB(printk("NCR53c406a BIOS found at 0x%x\n", (unsigned int) bios_base);
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);
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#endif /* USE_BIOS */
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#ifdef PORT_BASE
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if (!request_region(port_base, 0x10, "NCR53c406a")) /* ports already snatched */
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port_base = 0;
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#else /* autodetect */
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if (port_base) { /* LILO override */
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if (!request_region(port_base, 0x10, "NCR53c406a"))
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port_base = 0;
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} else {
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for (i = 0; i < PORT_COUNT && !port_base; i++) {
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if (!request_region(ports[i], 0x10, "NCR53c406a")) {
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DEB(printk("NCR53c406a: port 0x%x in use\n", ports[i]));
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} else {
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VDEB(printk("NCR53c406a: port 0x%x available\n", ports[i]));
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outb(C5_IMG, ports[i] + 0x0d); /* reg set 1 */
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if ((inb(ports[i] + 0x0e) ^ inb(ports[i] + 0x0e)) == 7 && (inb(ports[i] + 0x0e) ^ inb(ports[i] + 0x0e)) == 7 && (inb(ports[i] + 0x0e) & 0xf8) == 0x58) {
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port_base = ports[i];
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VDEB(printk("NCR53c406a: Sig register valid\n"));
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VDEB(printk("port_base=0x%x\n", port_base));
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break;
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}
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release_region(ports[i], 0x10);
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}
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}
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}
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#endif /* PORT_BASE */
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if (!port_base) { /* no ports found */
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printk("NCR53c406a: no available ports found\n");
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return 0;
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}
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DEB(printk("NCR53c406a detected\n"));
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calc_port_addr();
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chip_init();
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#ifndef IRQ_LEV
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if (irq_level < 0) { /* LILO override if >= 0 */
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irq_level = irq_probe();
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if (irq_level < 0) { /* Trouble */
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printk("NCR53c406a: IRQ problem, irq_level=%d, giving up\n", irq_level);
|
|
goto err_release;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
DEB(printk("NCR53c406a: using port_base 0x%x\n", port_base));
|
|
|
|
present = 1;
|
|
tpnt->proc_name = "NCR53c406a";
|
|
|
|
shpnt = scsi_register(tpnt, 0);
|
|
if (!shpnt) {
|
|
printk("NCR53c406a: Unable to register host, giving up.\n");
|
|
goto err_release;
|
|
}
|
|
|
|
if (irq_level > 0) {
|
|
if (request_irq(irq_level, do_NCR53c406a_intr, 0, "NCR53c406a", shpnt)) {
|
|
printk("NCR53c406a: unable to allocate IRQ %d\n", irq_level);
|
|
goto err_free_scsi;
|
|
}
|
|
tpnt->can_queue = 1;
|
|
DEB(printk("NCR53c406a: allocated IRQ %d\n", irq_level));
|
|
} else if (irq_level == 0) {
|
|
tpnt->can_queue = 0;
|
|
DEB(printk("NCR53c406a: No interrupts detected\n"));
|
|
printk("NCR53c406a driver no longer supports polling interface\n");
|
|
printk("Please email linux-scsi@vger.kernel.org\n");
|
|
|
|
#if USE_DMA
|
|
printk("NCR53c406a: No interrupts found and DMA mode defined. Giving up.\n");
|
|
#endif /* USE_DMA */
|
|
goto err_free_scsi;
|
|
} else {
|
|
DEB(printk("NCR53c406a: Shouldn't get here!\n"));
|
|
goto err_free_scsi;
|
|
}
|
|
|
|
#if USE_DMA
|
|
dma_chan = DMA_CHAN;
|
|
if (request_dma(dma_chan, "NCR53c406a") != 0) {
|
|
printk("NCR53c406a: unable to allocate DMA channel %d\n", dma_chan);
|
|
goto err_free_irq;
|
|
}
|
|
|
|
DEB(printk("Allocated DMA channel %d\n", dma_chan));
|
|
#endif /* USE_DMA */
|
|
|
|
shpnt->irq = irq_level;
|
|
shpnt->io_port = port_base;
|
|
shpnt->n_io_port = 0x10;
|
|
#if USE_DMA
|
|
shpnt->dma = dma_chan;
|
|
#endif
|
|
|
|
#if USE_DMA
|
|
sprintf(info_msg, "NCR53c406a at 0x%x, IRQ %d, DMA channel %d.", port_base, irq_level, dma_chan);
|
|
#else
|
|
sprintf(info_msg, "NCR53c406a at 0x%x, IRQ %d, %s PIO mode.", port_base, irq_level, fast_pio ? "fast" : "slow");
|
|
#endif
|
|
|
|
return (present);
|
|
|
|
#if USE_DMA
|
|
err_free_irq:
|
|
if (irq_level)
|
|
free_irq(irq_level, shpnt);
|
|
#endif
|
|
err_free_scsi:
|
|
scsi_unregister(shpnt);
|
|
err_release:
|
|
release_region(port_base, 0x10);
|
|
return 0;
|
|
}
|
|
|
|
static int NCR53c406a_release(struct Scsi_Host *shost)
|
|
{
|
|
if (shost->irq)
|
|
free_irq(shost->irq, NULL);
|
|
#ifdef USE_DMA
|
|
if (shost->dma_channel != 0xff)
|
|
free_dma(shost->dma_channel);
|
|
#endif
|
|
if (shost->io_port && shost->n_io_port)
|
|
release_region(shost->io_port, shost->n_io_port);
|
|
|
|
scsi_unregister(shost);
|
|
return 0;
|
|
}
|
|
|
|
/* called from init/main.c */
|
|
static int __init NCR53c406a_setup(char *str)
|
|
{
|
|
static size_t setup_idx = 0;
|
|
size_t i;
|
|
int ints[4];
|
|
|
|
DEB(printk("NCR53c406a: Setup called\n");
|
|
);
|
|
|
|
if (setup_idx >= PORT_COUNT - 1) {
|
|
printk("NCR53c406a: Setup called too many times. Bad LILO params?\n");
|
|
return 0;
|
|
}
|
|
get_options(str, 4, ints);
|
|
if (ints[0] < 1 || ints[0] > 3) {
|
|
printk("NCR53c406a: Malformed command line\n");
|
|
printk("NCR53c406a: Usage: ncr53c406a=<PORTBASE>[,<IRQ>[,<FASTPIO>]]\n");
|
|
return 0;
|
|
}
|
|
for (i = 0; i < PORT_COUNT && !port_base; i++)
|
|
if (ports[i] == ints[1]) {
|
|
port_base = ints[1];
|
|
DEB(printk("NCR53c406a: Specified port_base 0x%x\n", port_base);
|
|
)
|
|
}
|
|
if (!port_base) {
|
|
printk("NCR53c406a: Invalid PORTBASE 0x%x specified\n", ints[1]);
|
|
return 0;
|
|
}
|
|
|
|
if (ints[0] > 1) {
|
|
if (ints[2] == 0) {
|
|
irq_level = 0;
|
|
DEB(printk("NCR53c406a: Specified irq %d\n", irq_level);
|
|
)
|
|
} else
|
|
for (i = 0; i < INTR_COUNT && irq_level < 0; i++)
|
|
if (intrs[i] == ints[2]) {
|
|
irq_level = ints[2];
|
|
DEB(printk("NCR53c406a: Specified irq %d\n", port_base);
|
|
)
|
|
}
|
|
if (irq_level < 0)
|
|
printk("NCR53c406a: Invalid IRQ %d specified\n", ints[2]);
|
|
}
|
|
|
|
if (ints[0] > 2)
|
|
fast_pio = ints[3];
|
|
|
|
DEB(printk("NCR53c406a: port_base=0x%x, irq=%d, fast_pio=%d\n", port_base, irq_level, fast_pio);)
|
|
return 1;
|
|
}
|
|
|
|
__setup("ncr53c406a=", NCR53c406a_setup);
|
|
|
|
static const char *NCR53c406a_info(struct Scsi_Host *SChost)
|
|
{
|
|
DEB(printk("NCR53c406a_info called\n"));
|
|
return (info_msg);
|
|
}
|
|
|
|
#if 0
|
|
static void wait_intr(void)
|
|
{
|
|
unsigned long i = jiffies + WATCHDOG;
|
|
|
|
while (time_after(i, jiffies) && !(inb(STAT_REG) & 0xe0)) { /* wait for a pseudo-interrupt */
|
|
cpu_relax();
|
|
barrier();
|
|
}
|
|
|
|
if (time_before_eq(i, jiffies)) { /* Timed out */
|
|
rtrc(0);
|
|
current_SC->result = DID_TIME_OUT << 16;
|
|
current_SC->SCp.phase = idle;
|
|
current_SC->scsi_done(current_SC);
|
|
return;
|
|
}
|
|
|
|
NCR53c406a_intr(0, NULL, NULL);
|
|
}
|
|
#endif
|
|
|
|
static int NCR53c406a_queue(Scsi_Cmnd * SCpnt, void (*done) (Scsi_Cmnd *))
|
|
{
|
|
int i;
|
|
|
|
VDEB(printk("NCR53c406a_queue called\n"));
|
|
DEB(printk("cmd=%02x, cmd_len=%02x, target=%02x, lun=%02x, bufflen=%d\n", SCpnt->cmnd[0], SCpnt->cmd_len, SCpnt->target, SCpnt->lun, SCpnt->request_bufflen));
|
|
|
|
#if 0
|
|
VDEB(for (i = 0; i < SCpnt->cmd_len; i++)
|
|
printk("cmd[%d]=%02x ", i, SCpnt->cmnd[i]));
|
|
VDEB(printk("\n"));
|
|
#endif
|
|
|
|
current_SC = SCpnt;
|
|
current_SC->scsi_done = done;
|
|
current_SC->SCp.phase = command_ph;
|
|
current_SC->SCp.Status = 0;
|
|
current_SC->SCp.Message = 0;
|
|
|
|
/* We are locked here already by the mid layer */
|
|
REG0;
|
|
outb(scmd_id(SCpnt), DEST_ID); /* set destination */
|
|
outb(FLUSH_FIFO, CMD_REG); /* reset the fifos */
|
|
|
|
for (i = 0; i < SCpnt->cmd_len; i++) {
|
|
outb(SCpnt->cmnd[i], SCSI_FIFO);
|
|
}
|
|
outb(SELECT_NO_ATN, CMD_REG);
|
|
|
|
rtrc(1);
|
|
return 0;
|
|
}
|
|
|
|
static int NCR53c406a_host_reset(Scsi_Cmnd * SCpnt)
|
|
{
|
|
DEB(printk("NCR53c406a_reset called\n"));
|
|
|
|
spin_lock_irq(SCpnt->device->host->host_lock);
|
|
|
|
outb(C4_IMG, CONFIG4); /* Select reg set 0 */
|
|
outb(CHIP_RESET, CMD_REG);
|
|
outb(SCSI_NOP, CMD_REG); /* required after reset */
|
|
outb(SCSI_RESET, CMD_REG);
|
|
chip_init();
|
|
|
|
rtrc(2);
|
|
|
|
spin_unlock_irq(SCpnt->device->host->host_lock);
|
|
|
|
return SUCCESS;
|
|
}
|
|
|
|
static int NCR53c406a_biosparm(struct scsi_device *disk,
|
|
struct block_device *dev,
|
|
sector_t capacity, int *info_array)
|
|
{
|
|
int size;
|
|
|
|
DEB(printk("NCR53c406a_biosparm called\n"));
|
|
|
|
size = capacity;
|
|
info_array[0] = 64; /* heads */
|
|
info_array[1] = 32; /* sectors */
|
|
info_array[2] = size >> 11; /* cylinders */
|
|
if (info_array[2] > 1024) { /* big disk */
|
|
info_array[0] = 255;
|
|
info_array[1] = 63;
|
|
info_array[2] = size / (255 * 63);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t do_NCR53c406a_intr(int unused, void *dev_id,
|
|
struct pt_regs *regs)
|
|
{
|
|
unsigned long flags;
|
|
struct Scsi_Host *dev = dev_id;
|
|
|
|
spin_lock_irqsave(dev->host_lock, flags);
|
|
NCR53c406a_intr(0, dev_id, regs);
|
|
spin_unlock_irqrestore(dev->host_lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void NCR53c406a_intr(int unused, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
DEB(unsigned char fifo_size;
|
|
)
|
|
DEB(unsigned char seq_reg;
|
|
)
|
|
unsigned char status, int_reg;
|
|
#if USE_PIO
|
|
unsigned char pio_status;
|
|
struct scatterlist *sglist;
|
|
unsigned int sgcount;
|
|
#endif
|
|
|
|
VDEB(printk("NCR53c406a_intr called\n"));
|
|
|
|
#if USE_PIO
|
|
REG1;
|
|
pio_status = inb(PIO_STATUS);
|
|
#endif
|
|
REG0;
|
|
status = inb(STAT_REG);
|
|
DEB(seq_reg = inb(SEQ_REG));
|
|
int_reg = inb(INT_REG);
|
|
DEB(fifo_size = inb(FIFO_FLAGS) & 0x1f);
|
|
|
|
#if NCR53C406A_DEBUG
|
|
printk("status=%02x, seq_reg=%02x, int_reg=%02x, fifo_size=%02x", status, seq_reg, int_reg, fifo_size);
|
|
#if (USE_DMA)
|
|
printk("\n");
|
|
#else
|
|
printk(", pio=%02x\n", pio_status);
|
|
#endif /* USE_DMA */
|
|
#endif /* NCR53C406A_DEBUG */
|
|
|
|
if (int_reg & 0x80) { /* SCSI reset intr */
|
|
rtrc(3);
|
|
DEB(printk("NCR53c406a: reset intr received\n"));
|
|
current_SC->SCp.phase = idle;
|
|
current_SC->result = DID_RESET << 16;
|
|
current_SC->scsi_done(current_SC);
|
|
return;
|
|
}
|
|
#if USE_PIO
|
|
if (pio_status & 0x80) {
|
|
printk("NCR53C406A: Warning: PIO error!\n");
|
|
current_SC->SCp.phase = idle;
|
|
current_SC->result = DID_ERROR << 16;
|
|
current_SC->scsi_done(current_SC);
|
|
return;
|
|
}
|
|
#endif /* USE_PIO */
|
|
|
|
if (status & 0x20) { /* Parity error */
|
|
printk("NCR53c406a: Warning: parity error!\n");
|
|
current_SC->SCp.phase = idle;
|
|
current_SC->result = DID_PARITY << 16;
|
|
current_SC->scsi_done(current_SC);
|
|
return;
|
|
}
|
|
|
|
if (status & 0x40) { /* Gross error */
|
|
printk("NCR53c406a: Warning: gross error!\n");
|
|
current_SC->SCp.phase = idle;
|
|
current_SC->result = DID_ERROR << 16;
|
|
current_SC->scsi_done(current_SC);
|
|
return;
|
|
}
|
|
|
|
if (int_reg & 0x20) { /* Disconnect */
|
|
DEB(printk("NCR53c406a: disconnect intr received\n"));
|
|
if (current_SC->SCp.phase != message_in) { /* Unexpected disconnect */
|
|
current_SC->result = DID_NO_CONNECT << 16;
|
|
} else { /* Command complete, return status and message */
|
|
current_SC->result = (current_SC->SCp.Status & 0xff)
|
|
| ((current_SC->SCp.Message & 0xff) << 8) | (DID_OK << 16);
|
|
}
|
|
|
|
rtrc(0);
|
|
current_SC->SCp.phase = idle;
|
|
current_SC->scsi_done(current_SC);
|
|
return;
|
|
}
|
|
|
|
switch (status & 0x07) { /* scsi phase */
|
|
case 0x00: /* DATA-OUT */
|
|
if (int_reg & 0x10) { /* Target requesting info transfer */
|
|
rtrc(5);
|
|
current_SC->SCp.phase = data_out;
|
|
VDEB(printk("NCR53c406a: Data-Out phase\n"));
|
|
outb(FLUSH_FIFO, CMD_REG);
|
|
LOAD_DMA_COUNT(current_SC->request_bufflen); /* Max transfer size */
|
|
#if USE_DMA /* No s/g support for DMA */
|
|
NCR53c406a_dma_write(current_SC->request_buffer, current_SC->request_bufflen);
|
|
#endif /* USE_DMA */
|
|
outb(TRANSFER_INFO | DMA_OP, CMD_REG);
|
|
#if USE_PIO
|
|
if (!current_SC->use_sg) /* Don't use scatter-gather */
|
|
NCR53c406a_pio_write(current_SC->request_buffer, current_SC->request_bufflen);
|
|
else { /* use scatter-gather */
|
|
sgcount = current_SC->use_sg;
|
|
sglist = current_SC->request_buffer;
|
|
while (sgcount--) {
|
|
NCR53c406a_pio_write(page_address(sglist->page) + sglist->offset, sglist->length);
|
|
sglist++;
|
|
}
|
|
}
|
|
REG0;
|
|
#endif /* USE_PIO */
|
|
}
|
|
break;
|
|
|
|
case 0x01: /* DATA-IN */
|
|
if (int_reg & 0x10) { /* Target requesting info transfer */
|
|
rtrc(6);
|
|
current_SC->SCp.phase = data_in;
|
|
VDEB(printk("NCR53c406a: Data-In phase\n"));
|
|
outb(FLUSH_FIFO, CMD_REG);
|
|
LOAD_DMA_COUNT(current_SC->request_bufflen); /* Max transfer size */
|
|
#if USE_DMA /* No s/g support for DMA */
|
|
NCR53c406a_dma_read(current_SC->request_buffer, current_SC->request_bufflen);
|
|
#endif /* USE_DMA */
|
|
outb(TRANSFER_INFO | DMA_OP, CMD_REG);
|
|
#if USE_PIO
|
|
if (!current_SC->use_sg) /* Don't use scatter-gather */
|
|
NCR53c406a_pio_read(current_SC->request_buffer, current_SC->request_bufflen);
|
|
else { /* Use scatter-gather */
|
|
sgcount = current_SC->use_sg;
|
|
sglist = current_SC->request_buffer;
|
|
while (sgcount--) {
|
|
NCR53c406a_pio_read(page_address(sglist->page) + sglist->offset, sglist->length);
|
|
sglist++;
|
|
}
|
|
}
|
|
REG0;
|
|
#endif /* USE_PIO */
|
|
}
|
|
break;
|
|
|
|
case 0x02: /* COMMAND */
|
|
current_SC->SCp.phase = command_ph;
|
|
printk("NCR53c406a: Warning: Unknown interrupt occurred in command phase!\n");
|
|
break;
|
|
|
|
case 0x03: /* STATUS */
|
|
rtrc(7);
|
|
current_SC->SCp.phase = status_ph;
|
|
VDEB(printk("NCR53c406a: Status phase\n"));
|
|
outb(FLUSH_FIFO, CMD_REG);
|
|
outb(INIT_CMD_COMPLETE, CMD_REG);
|
|
break;
|
|
|
|
case 0x04: /* Reserved */
|
|
case 0x05: /* Reserved */
|
|
printk("NCR53c406a: WARNING: Reserved phase!!!\n");
|
|
break;
|
|
|
|
case 0x06: /* MESSAGE-OUT */
|
|
DEB(printk("NCR53c406a: Message-Out phase\n"));
|
|
current_SC->SCp.phase = message_out;
|
|
outb(SET_ATN, CMD_REG); /* Reject the message */
|
|
outb(MSG_ACCEPT, CMD_REG);
|
|
break;
|
|
|
|
case 0x07: /* MESSAGE-IN */
|
|
rtrc(4);
|
|
VDEB(printk("NCR53c406a: Message-In phase\n"));
|
|
current_SC->SCp.phase = message_in;
|
|
|
|
current_SC->SCp.Status = inb(SCSI_FIFO);
|
|
current_SC->SCp.Message = inb(SCSI_FIFO);
|
|
|
|
VDEB(printk("SCSI FIFO size=%d\n", inb(FIFO_FLAGS) & 0x1f));
|
|
DEB(printk("Status = %02x Message = %02x\n", current_SC->SCp.Status, current_SC->SCp.Message));
|
|
|
|
if (current_SC->SCp.Message == SAVE_POINTERS || current_SC->SCp.Message == DISCONNECT) {
|
|
outb(SET_ATN, CMD_REG); /* Reject message */
|
|
DEB(printk("Discarding SAVE_POINTERS message\n"));
|
|
}
|
|
outb(MSG_ACCEPT, CMD_REG);
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifndef IRQ_LEV
|
|
static int irq_probe(void)
|
|
{
|
|
int irqs, irq;
|
|
unsigned long i;
|
|
|
|
inb(INT_REG); /* clear the interrupt register */
|
|
irqs = probe_irq_on();
|
|
|
|
/* Invalid command will cause an interrupt */
|
|
REG0;
|
|
outb(0xff, CMD_REG);
|
|
|
|
/* Wait for the interrupt to occur */
|
|
i = jiffies + WATCHDOG;
|
|
while (time_after(i, jiffies) && !(inb(STAT_REG) & 0x80))
|
|
barrier();
|
|
if (time_before_eq(i, jiffies)) { /* Timed out, must be hardware trouble */
|
|
probe_irq_off(irqs);
|
|
return -1;
|
|
}
|
|
|
|
irq = probe_irq_off(irqs);
|
|
|
|
/* Kick the chip */
|
|
outb(CHIP_RESET, CMD_REG);
|
|
outb(SCSI_NOP, CMD_REG);
|
|
chip_init();
|
|
|
|
return irq;
|
|
}
|
|
#endif /* IRQ_LEV */
|
|
|
|
static void chip_init(void)
|
|
{
|
|
REG1;
|
|
#if USE_DMA
|
|
outb(0x00, PIO_STATUS);
|
|
#else /* USE_PIO */
|
|
outb(0x01, PIO_STATUS);
|
|
#endif
|
|
outb(0x00, PIO_FLAG);
|
|
|
|
outb(C4_IMG, CONFIG4); /* REG0; */
|
|
outb(C3_IMG, CONFIG3);
|
|
outb(C2_IMG, CONFIG2);
|
|
outb(C1_IMG, CONFIG1);
|
|
|
|
outb(0x05, CLKCONV); /* clock conversion factor */
|
|
outb(0x9C, SRTIMOUT); /* Selection timeout */
|
|
outb(0x05, SYNCPRD); /* Synchronous transfer period */
|
|
outb(SYNC_MODE, SYNCOFF); /* synchronous mode */
|
|
}
|
|
|
|
static void __init calc_port_addr(void)
|
|
{
|
|
/* Control Register Set 0 */
|
|
TC_LSB = (port_base + 0x00);
|
|
TC_MSB = (port_base + 0x01);
|
|
SCSI_FIFO = (port_base + 0x02);
|
|
CMD_REG = (port_base + 0x03);
|
|
STAT_REG = (port_base + 0x04);
|
|
DEST_ID = (port_base + 0x04);
|
|
INT_REG = (port_base + 0x05);
|
|
SRTIMOUT = (port_base + 0x05);
|
|
SEQ_REG = (port_base + 0x06);
|
|
SYNCPRD = (port_base + 0x06);
|
|
FIFO_FLAGS = (port_base + 0x07);
|
|
SYNCOFF = (port_base + 0x07);
|
|
CONFIG1 = (port_base + 0x08);
|
|
CLKCONV = (port_base + 0x09);
|
|
/* TESTREG = (port_base+0x0A); */
|
|
CONFIG2 = (port_base + 0x0B);
|
|
CONFIG3 = (port_base + 0x0C);
|
|
CONFIG4 = (port_base + 0x0D);
|
|
TC_HIGH = (port_base + 0x0E);
|
|
/* FIFO_BOTTOM = (port_base+0x0F); */
|
|
|
|
/* Control Register Set 1 */
|
|
/* JUMPER_SENSE = (port_base+0x00); */
|
|
/* SRAM_PTR = (port_base+0x01); */
|
|
/* SRAM_DATA = (port_base+0x02); */
|
|
PIO_FIFO = (port_base + 0x04);
|
|
/* PIO_FIFO1 = (port_base+0x05); */
|
|
/* PIO_FIFO2 = (port_base+0x06); */
|
|
/* PIO_FIFO3 = (port_base+0x07); */
|
|
PIO_STATUS = (port_base + 0x08);
|
|
/* ATA_CMD = (port_base+0x09); */
|
|
/* ATA_ERR = (port_base+0x0A); */
|
|
PIO_FLAG = (port_base + 0x0B);
|
|
CONFIG5 = (port_base + 0x0D);
|
|
/* SIGNATURE = (port_base+0x0E); */
|
|
/* CONFIG6 = (port_base+0x0F); */
|
|
}
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
/* NOTE: scatter-gather support only works in PIO mode.
|
|
* Use SG_NONE if DMA mode is enabled!
|
|
*/
|
|
|
|
static struct scsi_host_template driver_template =
|
|
{
|
|
.proc_name = "NCR53c406a" /* proc_name */,
|
|
.name = "NCR53c406a" /* name */,
|
|
.detect = NCR53c406a_detect /* detect */,
|
|
.release = NCR53c406a_release,
|
|
.info = NCR53c406a_info /* info */,
|
|
.queuecommand = NCR53c406a_queue /* queuecommand */,
|
|
.eh_host_reset_handler = NCR53c406a_host_reset /* reset */,
|
|
.bios_param = NCR53c406a_biosparm /* biosparm */,
|
|
.can_queue = 1 /* can_queue */,
|
|
.this_id = 7 /* SCSI ID of the chip */,
|
|
.sg_tablesize = 32 /*SG_ALL*/ /*SG_NONE*/,
|
|
.cmd_per_lun = 1 /* commands per lun */,
|
|
.unchecked_isa_dma = 1 /* unchecked_isa_dma */,
|
|
.use_clustering = ENABLE_CLUSTERING
|
|
};
|
|
|
|
#include "scsi_module.c"
|
|
|
|
/*
|
|
* Overrides for Emacs so that we get a uniform tabbing style.
|
|
* Emacs will notice this stuff at the end of the file and automatically
|
|
* adjust the settings for this buffer only. This must remain at the end
|
|
* of the file.
|
|
* ---------------------------------------------------------------------------
|
|
* Local variables:
|
|
* c-indent-level: 4
|
|
* c-brace-imaginary-offset: 0
|
|
* c-brace-offset: -4
|
|
* c-argdecl-indent: 4
|
|
* c-label-offset: -4
|
|
* c-continued-statement-offset: 4
|
|
* c-continued-brace-offset: 0
|
|
* indent-tabs-mode: nil
|
|
* tab-width: 8
|
|
* End:
|
|
*/
|