d09ee9687e
We could run out of space under under 4g, but devices under transparent bridges can use 64bit resources, so keep trying on the parent bus until we hit a non-transparent bridge. Impact: better support for assigning unassigned resources Reviewed-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
331 lines
7.7 KiB
C
331 lines
7.7 KiB
C
/*
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* drivers/pci/setup-res.c
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*
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* Extruded from code written by
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* Dave Rusling (david.rusling@reo.mts.dec.com)
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* David Mosberger (davidm@cs.arizona.edu)
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* David Miller (davem@redhat.com)
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*
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* Support routines for initializing a PCI subsystem.
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*/
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/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
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/*
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* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* Resource sorting
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/cache.h>
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#include <linux/slab.h>
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#include "pci.h"
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void pci_update_resource(struct pci_dev *dev, int resno)
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{
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struct pci_bus_region region;
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u32 new, check, mask;
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int reg;
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enum pci_bar_type type;
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struct resource *res = dev->resource + resno;
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/*
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* Ignore resources for unimplemented BARs and unused resource slots
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* for 64 bit BARs.
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*/
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if (!res->flags)
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return;
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/*
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* Ignore non-moveable resources. This might be legacy resources for
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* which no functional BAR register exists or another important
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* system resource we shouldn't move around.
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*/
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if (res->flags & IORESOURCE_PCI_FIXED)
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return;
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pcibios_resource_to_bus(dev, ®ion, res);
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dev_dbg(&dev->dev, "BAR %d: got res %pR bus [%#llx-%#llx] "
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"flags %#lx\n", resno, res,
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(unsigned long long)region.start,
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(unsigned long long)region.end,
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(unsigned long)res->flags);
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new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
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if (res->flags & IORESOURCE_IO)
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mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
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else
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mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
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reg = pci_resource_bar(dev, resno, &type);
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if (!reg)
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return;
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if (type != pci_bar_unknown) {
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if (!(res->flags & IORESOURCE_ROM_ENABLE))
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return;
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new |= PCI_ROM_ADDRESS_ENABLE;
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}
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pci_write_config_dword(dev, reg, new);
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pci_read_config_dword(dev, reg, &check);
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if ((new ^ check) & mask) {
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dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
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resno, new, check);
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}
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if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
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new = region.start >> 16 >> 16;
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pci_write_config_dword(dev, reg + 4, new);
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pci_read_config_dword(dev, reg + 4, &check);
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if (check != new) {
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dev_err(&dev->dev, "BAR %d: error updating "
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"(high %#08x != %#08x)\n", resno, new, check);
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}
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}
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res->flags &= ~IORESOURCE_UNSET;
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dev_dbg(&dev->dev, "BAR %d: moved to bus [%#llx-%#llx] flags %#lx\n",
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resno, (unsigned long long)region.start,
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(unsigned long long)region.end, res->flags);
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}
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int pci_claim_resource(struct pci_dev *dev, int resource)
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{
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struct resource *res = &dev->resource[resource];
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struct resource *root = NULL;
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char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
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int err;
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root = pcibios_select_root(dev, res);
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err = -EINVAL;
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if (root != NULL)
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err = insert_resource(root, res);
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if (err) {
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dev_err(&dev->dev, "BAR %d: %s of %s %pR\n",
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resource,
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root ? "address space collision on" :
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"no parent found for",
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dtype, res);
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}
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return err;
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}
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#ifdef CONFIG_PCI_QUIRKS
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void pci_disable_bridge_window(struct pci_dev *dev)
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{
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dev_dbg(&dev->dev, "Disabling bridge window.\n");
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/* MMIO Base/Limit */
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pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
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/* Prefetchable MMIO Base/Limit */
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pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
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pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
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pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
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}
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#endif /* CONFIG_PCI_QUIRKS */
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static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
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int resno)
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{
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struct resource *res = dev->resource + resno;
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resource_size_t size, min, align;
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int ret;
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size = resource_size(res);
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min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
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align = resource_alignment(res);
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/* First, try exact prefetching match.. */
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ret = pci_bus_alloc_resource(bus, res, size, align, min,
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IORESOURCE_PREFETCH,
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pcibios_align_resource, dev);
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if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
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/*
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* That failed.
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*
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* But a prefetching area can handle a non-prefetching
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* window (it will just not perform as well).
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*/
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ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
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pcibios_align_resource, dev);
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}
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if (!ret) {
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res->flags &= ~IORESOURCE_STARTALIGN;
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if (resno < PCI_BRIDGE_RESOURCES)
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pci_update_resource(dev, resno);
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}
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return ret;
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}
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int pci_assign_resource(struct pci_dev *dev, int resno)
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{
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struct resource *res = dev->resource + resno;
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resource_size_t align;
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struct pci_bus *bus;
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int ret;
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align = resource_alignment(res);
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if (!align) {
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dev_info(&dev->dev, "BAR %d: can't allocate resource (bogus "
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"alignment) %pR flags %#lx\n",
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resno, res, res->flags);
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return -EINVAL;
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}
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bus = dev->bus;
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while ((ret = __pci_assign_resource(bus, dev, resno))) {
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if (bus->parent && bus->self->transparent)
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bus = bus->parent;
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else
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bus = NULL;
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if (bus)
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continue;
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break;
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}
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if (ret)
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dev_info(&dev->dev, "BAR %d: can't allocate %s resource %pR\n",
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resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res);
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return ret;
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}
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#if 0
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int pci_assign_resource_fixed(struct pci_dev *dev, int resno)
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{
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struct pci_bus *bus = dev->bus;
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struct resource *res = dev->resource + resno;
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unsigned int type_mask;
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int i, ret = -EBUSY;
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type_mask = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH;
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for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
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struct resource *r = bus->resource[i];
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if (!r)
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continue;
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/* type_mask must match */
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if ((res->flags ^ r->flags) & type_mask)
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continue;
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ret = request_resource(r, res);
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if (ret == 0)
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break;
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}
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if (ret) {
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dev_err(&dev->dev, "BAR %d: can't allocate %s resource %pR\n",
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resno, res->flags & IORESOURCE_IO ? "I/O" : "mem", res);
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} else if (resno < PCI_BRIDGE_RESOURCES) {
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pci_update_resource(dev, resno);
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_assign_resource_fixed);
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#endif
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/* Sort resources by alignment */
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void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
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{
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r;
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struct resource_list *list, *tmp;
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resource_size_t r_align;
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r = &dev->resource[i];
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if (r->flags & IORESOURCE_PCI_FIXED)
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continue;
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if (!(r->flags) || r->parent)
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continue;
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r_align = resource_alignment(r);
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if (!r_align) {
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dev_warn(&dev->dev, "BAR %d: bogus alignment "
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"%pR flags %#lx\n",
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i, r, r->flags);
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continue;
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}
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for (list = head; ; list = list->next) {
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resource_size_t align = 0;
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struct resource_list *ln = list->next;
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if (ln)
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align = resource_alignment(ln->res);
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if (r_align > align) {
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tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
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if (!tmp)
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panic("pdev_sort_resources(): "
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"kmalloc() failed!\n");
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tmp->next = ln;
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tmp->res = r;
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tmp->dev = dev;
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list->next = tmp;
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break;
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}
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}
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}
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}
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int pci_enable_resources(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int i;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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if (!(mask & (1 << i)))
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continue;
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r = &dev->resource[i];
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if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
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continue;
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if ((i == PCI_ROM_RESOURCE) &&
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(!(r->flags & IORESOURCE_ROM_ENABLE)))
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continue;
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if (!r->parent) {
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dev_err(&dev->dev, "device not available because of "
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"BAR %d %pR collisions\n", i, r);
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
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old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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