d1b4cc3ec5
We want to stop sharing stuff with gx1fb; it makes little sense. There were
fields in geodefb_par that weren't being used, there was little point to the
DC/VP ops callbacks, etc. This implements the following:
- Create gxfb_par (based on geodefb_par), place it in gxfb.h
- Drop display_gx.h and video_gx.h. The last few patches moved most
stuff into gxfb.h anyways, so there was very little left.
- Drop the geode_{dc,vid}_ops stuff. Un-static functions, add
declarations to gxfb.h.
Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Jordan Crouse <jordan.crouse@amd.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
168 lines
4.5 KiB
C
168 lines
4.5 KiB
C
/*
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* Geode GX display controller.
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*
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* Copyright (C) 2005 Arcom Control Systems Ltd.
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*
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* Portions from AMD's original 2.4 driver:
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* Copyright (C) 2004 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by * the
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* Free Software Foundation; either version 2 of the License, or * (at your
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* option) any later version.
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*/
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#include <linux/spinlock.h>
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#include <linux/fb.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/div64.h>
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#include <asm/delay.h>
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#include "gxfb.h"
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unsigned int gx_frame_buffer_size(void)
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{
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unsigned int val;
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/* FB size is reported by a virtual register */
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/* Virtual register class = 0x02 */
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/* VG_MEM_SIZE(512Kb units) = 0x00 */
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outw(0xFC53, 0xAC1C);
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outw(0x0200, 0xAC1C);
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val = (unsigned int)(inw(0xAC1E)) & 0xFFl;
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return (val << 19);
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}
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int gx_line_delta(int xres, int bpp)
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{
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/* Must be a multiple of 8 bytes. */
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return (xres * (bpp >> 3) + 7) & ~0x7;
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}
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void gx_set_mode(struct fb_info *info)
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{
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struct gxfb_par *par = info->par;
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u32 gcfg, dcfg;
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int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
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int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
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/* Unlock the display controller registers. */
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write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
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gcfg = read_dc(par, DC_GENERAL_CFG);
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dcfg = read_dc(par, DC_DISPLAY_CFG);
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/* Disable the timing generator. */
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dcfg &= ~DC_DISPLAY_CFG_TGEN;
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write_dc(par, DC_DISPLAY_CFG, dcfg);
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/* Wait for pending memory requests before disabling the FIFO load. */
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udelay(100);
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/* Disable FIFO load and compression. */
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gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
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DC_GENERAL_CFG_DECE);
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write_dc(par, DC_GENERAL_CFG, gcfg);
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/* Setup DCLK and its divisor. */
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gx_set_dclk_frequency(info);
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/*
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* Setup new mode.
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*/
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/* Clear all unused feature bits. */
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gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
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dcfg = 0;
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/* Set FIFO priority (default 6/5) and enable. */
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/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
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gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
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(5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
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/* Framebuffer start offset. */
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write_dc(par, DC_FB_ST_OFFSET, 0);
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/* Line delta and line buffer length. */
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write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
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write_dc(par, DC_LINE_SIZE,
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((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
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/* Enable graphics and video data and unmask address lines. */
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dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
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DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
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/* Set pixel format. */
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switch (info->var.bits_per_pixel) {
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case 8:
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
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break;
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case 16:
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
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break;
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case 32:
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
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dcfg |= DC_DISPLAY_CFG_PALB;
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break;
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}
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/* Enable timing generator. */
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dcfg |= DC_DISPLAY_CFG_TGEN;
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/* Horizontal and vertical timings. */
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hactive = info->var.xres;
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hblankstart = hactive;
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hsyncstart = hblankstart + info->var.right_margin;
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hsyncend = hsyncstart + info->var.hsync_len;
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hblankend = hsyncend + info->var.left_margin;
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htotal = hblankend;
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vactive = info->var.yres;
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vblankstart = vactive;
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vsyncstart = vblankstart + info->var.lower_margin;
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vsyncend = vsyncstart + info->var.vsync_len;
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vblankend = vsyncend + info->var.upper_margin;
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vtotal = vblankend;
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write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
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((htotal - 1) << 16));
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write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
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((hblankend - 1) << 16));
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write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
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((hsyncend - 1) << 16));
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write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
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((vtotal - 1) << 16));
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write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
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((vblankend - 1) << 16));
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write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
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((vsyncend - 1) << 16));
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/* Write final register values. */
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write_dc(par, DC_DISPLAY_CFG, dcfg);
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write_dc(par, DC_GENERAL_CFG, gcfg);
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gx_configure_display(info);
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/* Relock display controller registers */
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write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
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}
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void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
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unsigned red, unsigned green, unsigned blue)
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{
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struct gxfb_par *par = info->par;
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int val;
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/* Hardware palette is in RGB 8-8-8 format. */
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val = (red << 8) & 0xff0000;
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val |= (green) & 0x00ff00;
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val |= (blue >> 8) & 0x0000ff;
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write_dc(par, DC_PAL_ADDRESS, regno);
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write_dc(par, DC_PAL_DATA, val);
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}
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