d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
/*
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* linux/arch/m32r/kernel/setup_m32104ut.c
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*
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* Setup routines for M32104UT Board
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*
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* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Mamoru Sakugawa,
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* Naoto Sugai, Hayato Fujiwara
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*/
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#include <linux/config.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
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icu_data_t icu_data[NR_IRQS];
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static void disable_m32104ut_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
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outl(data, port);
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}
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static void enable_m32104ut_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
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outl(data, port);
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}
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static void mask_and_ack_m32104ut(unsigned int irq)
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{
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disable_m32104ut_irq(irq);
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}
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static void end_m32104ut_irq(unsigned int irq)
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{
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enable_m32104ut_irq(irq);
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}
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static unsigned int startup_m32104ut_irq(unsigned int irq)
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{
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enable_m32104ut_irq(irq);
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return (0);
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}
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static void shutdown_m32104ut_irq(unsigned int irq)
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{
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unsigned long port;
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port = irq2port(irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct hw_interrupt_type m32104ut_irq_type =
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{
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.typename = "M32104UT-IRQ",
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.startup = startup_m32104ut_irq,
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.shutdown = shutdown_m32104ut_irq,
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.enable = enable_m32104ut_irq,
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.disable = disable_m32104ut_irq,
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.ack = mask_and_ack_m32104ut,
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.end = end_m32104ut_irq
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};
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void __init init_IRQ(void)
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{
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static int once = 0;
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if (once)
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return;
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else
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once++;
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#if defined(CONFIG_SMC91X)
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/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
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irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_INT0].action = 0;
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irq_desc[M32R_IRQ_INT0].depth = 1;
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icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
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disable_m32104ut_irq(M32R_IRQ_INT0);
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#endif /* CONFIG_SMC91X */
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/* MFT2 : system timer */
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irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_MFT2].action = 0;
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irq_desc[M32R_IRQ_MFT2].depth = 1;
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_m32104ut_irq(M32R_IRQ_MFT2);
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#ifdef CONFIG_SERIAL_M32R_SIO
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/* SIO0_R : uart receive data */
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irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_SIO0_R].action = 0;
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irq_desc[M32R_IRQ_SIO0_R].depth = 1;
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icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
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disable_m32104ut_irq(M32R_IRQ_SIO0_R);
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/* SIO0_S : uart send data */
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irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type;
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irq_desc[M32R_IRQ_SIO0_S].action = 0;
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irq_desc[M32R_IRQ_SIO0_S].depth = 1;
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icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
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disable_m32104ut_irq(M32R_IRQ_SIO0_S);
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#endif /* CONFIG_SERIAL_M32R_SIO */
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}
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#if defined(CONFIG_SMC91X)
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#define LAN_IOSTART 0x300
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#define LAN_IOEND 0x320
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = (LAN_IOSTART),
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.end = (LAN_IOEND),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = M32R_IRQ_INT0,
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.end = M32R_IRQ_INT0,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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#endif
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static int __init platform_init(void)
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{
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#if defined(CONFIG_SMC91X)
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platform_device_register(&smc91x_device);
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#endif
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return 0;
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}
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arch_initcall(platform_init);
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