0ebfff1491
This adds the new irq remapper core and removes the old one. Because there are some fundamental conflicts with the old code, like the value of NO_IRQ which I'm now setting to 0 (as per discussions with Linus), etc..., this commit also changes the relevant platform and driver code over to use the new remapper (so as not to cause difficulties later in bisecting). This patch removes the old pre-parsing of the open firmware interrupt tree along with all the bogus assumptions it made to try to renumber interrupts according to the platform. This is all to be handled by the new code now. For the pSeries XICS interrupt controller, a single remapper host is created for the whole machine regardless of how many interrupt presentation and source controllers are found, and it's set to match any device node that isn't a 8259. That works fine on pSeries and avoids having to deal with some of the complexities of split source controllers vs. presentation controllers in the pSeries device trees. The powerpc i8259 PIC driver now always requests the legacy interrupt range. It also has the feature of being able to match any device node (including NULL) if passed no device node as an input. That will help porting over platforms with broken device-trees like Pegasos who don't have a proper interrupt tree. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
#ifndef ASM_CELL_PIC_H
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#define ASM_CELL_PIC_H
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#ifdef __KERNEL__
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/*
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* Mapping of IIC pending bits into per-node
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* interrupt numbers.
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*
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* IRQ FF CC SS PP FF CC SS PP Description
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*
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* 00-3f 80 02 +0 00 - 80 02 +0 3f South Bridge
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* 00-3f 80 02 +b 00 - 80 02 +b 3f South Bridge
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* 41-4a 80 00 +1 ** - 80 00 +a ** SPU Class 0
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* 51-5a 80 01 +1 ** - 80 01 +a ** SPU Class 1
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* 61-6a 80 02 +1 ** - 80 02 +a ** SPU Class 2
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* 70-7f C0 ** ** 00 - C0 ** ** 0f IPI
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*
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* F flags
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* C class
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* S source
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* P Priority
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* + node number
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* * don't care
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*
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* A node consists of a Cell Broadband Engine and an optional
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* south bridge device providing a maximum of 64 IRQs.
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* The south bridge may be connected to either IOIF0
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* or IOIF1.
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* Each SPE is represented as three IRQ lines, one per
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* interrupt class.
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* 16 IRQ numbers are reserved for inter processor
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* interruptions, although these are only used in the
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* range of the first node.
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*
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* This scheme needs 128 IRQ numbers per BIF node ID,
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* which means that with the total of 512 lines
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* available, we can have a maximum of four nodes.
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*/
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enum {
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IIC_IRQ_INVALID = 0xff,
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IIC_IRQ_MAX = 0x3f,
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IIC_IRQ_EXT_IOIF0 = 0x20,
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IIC_IRQ_EXT_IOIF1 = 0x2b,
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IIC_IRQ_IPI0 = 0x40,
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IIC_NUM_IPIS = 0x10, /* IRQs reserved for IPI */
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IIC_SOURCE_COUNT = 0x50,
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};
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extern void iic_init_IRQ(void);
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extern void iic_cause_IPI(int cpu, int mesg);
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extern void iic_request_IPIs(void);
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extern void iic_setup_cpu(void);
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extern u8 iic_get_target_id(int cpu);
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extern struct irq_host *iic_get_irq_host(int node);
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extern void spider_init_IRQ(void);
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#endif
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#endif /* ASM_CELL_PIC_H */
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