53c2df2f4e
Many RTC routines were not protected against each other, so there are
potential races, for example, ntp-update against /dev/rtc. This patch
fixes them using rtc_lock.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
477 lines
14 KiB
C
477 lines
14 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Momentum Computer Jaguar-ATX board dependent boot routines
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*
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* Copyright (C) 1996, 1997, 2001, 2004 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2000 RidgeRun, Inc.
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* Copyright (C) 2001 Red Hat, Inc.
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* Copyright (C) 2002 Momentum Computer
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*
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* Author: Matthew Dharm, Momentum Computer
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* mdharm@momenco.com
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*
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* Louis Hamilton, Red Hat, Inc.
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* hamilton@redhat.com [MIPS64 modifications]
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*
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/bcd.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/swap.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/vmalloc.h>
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#include <asm/time.h>
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#include <asm/bootinfo.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/reboot.h>
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#include <asm/tlbflush.h>
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#include <asm/mv64340.h>
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#include "jaguar_atx_fpga.h"
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extern unsigned long mv64340_sram_base;
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unsigned long cpu_clock;
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/* These functions are used for rebooting or halting the machine*/
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extern void momenco_jaguar_restart(char *command);
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extern void momenco_jaguar_halt(void);
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extern void momenco_jaguar_power_off(void);
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void momenco_time_init(void);
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static char reset_reason;
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static inline unsigned long ENTRYLO(unsigned long paddr)
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{
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return ((paddr & PAGE_MASK) |
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(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
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_CACHE_UNCACHED)) >> 6;
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}
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void __init bus_error_init(void) { /* nothing */ }
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/*
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* Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
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* to be hit on every IRQ anyway - there's absolutely no point in letting it be
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* a random TLB entry, as it'll just cause needless churning of the TLB. And we
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* use the other half for the serial port, which is just a PITA otherwise :)
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*
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* Device Physical Virtual
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* MV64340 Internal Regs 0xf4000000 0xf4000000
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* Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
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* NVRAM (CS1) 0xfc800000 0xfc800000
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* UARTs (CS2) 0xfd000000 0xfd000000
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* Internal SRAM 0xfe000000 0xfe000000
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* M-Systems DOC (CS3) 0xff000000 0xff000000
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*/
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static __init void wire_stupidity_into_tlb(void)
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{
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#ifdef CONFIG_32BIT
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write_c0_wired(0);
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local_flush_tlb_all();
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/* marvell and extra space */
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add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
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0xf4000000UL, PM_64K);
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/* fpga, rtc, and uart */
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add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
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0xfc000000UL, PM_16M);
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// /* m-sys and internal SRAM */
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// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
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// 0xfe000000UL, PM_16M);
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marvell_base = 0xf4000000;
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//mv64340_sram_base = 0xfe000000; /* Currently unused */
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#endif
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}
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unsigned long marvell_base = 0xf4000000L;
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unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
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unsigned long uart_base = 0xfd000000L;
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static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
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EXPORT_SYMBOL(marvell_base);
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static __init int per_cpu_mappings(void)
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{
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marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
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ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
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uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
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rtc_base = ioremap(0xfc000000UL, 0x8000);
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// ioremap(0xfe000000, 32 << 20);
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write_c0_wired(0);
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local_flush_tlb_all();
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ja_setup_console();
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return 0;
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}
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arch_initcall(per_cpu_mappings);
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unsigned long m48t37y_get_time(void)
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{
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unsigned int year, month, day, hour, min, sec;
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unsigned long flags;
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spin_lock_irqsave(&rtc_lock, flags);
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/* stop the update */
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rtc_base[0x7ff8] = 0x40;
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year = BCD2BIN(rtc_base[0x7fff]);
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year += BCD2BIN(rtc_base[0x7ff1]) * 100;
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month = BCD2BIN(rtc_base[0x7ffe]);
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day = BCD2BIN(rtc_base[0x7ffd]);
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hour = BCD2BIN(rtc_base[0x7ffb]);
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min = BCD2BIN(rtc_base[0x7ffa]);
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sec = BCD2BIN(rtc_base[0x7ff9]);
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/* start the update */
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rtc_base[0x7ff8] = 0x00;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return mktime(year, month, day, hour, min, sec);
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}
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int m48t37y_set_time(unsigned long sec)
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{
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struct rtc_time tm;
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unsigned long flags;
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/* convert to a more useful format -- note months count from 0 */
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to_tm(sec, &tm);
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tm.tm_mon += 1;
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spin_lock_irqsave(&rtc_lock, flags);
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/* enable writing */
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rtc_base[0x7ff8] = 0x80;
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/* year */
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rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
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rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
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/* month */
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rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
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/* day */
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rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
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/* hour/min/sec */
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rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
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rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
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rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
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/* day of week -- not really used, but let's keep it up-to-date */
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rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
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/* disable writing */
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rtc_base[0x7ff8] = 0x00;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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void momenco_timer_setup(struct irqaction *irq)
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{
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setup_irq(8, irq);
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}
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/*
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* Ugly but the least of all evils. TLB initialization did flush the TLB so
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* We need to setup mappings again before we can touch the RTC.
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*/
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void momenco_time_init(void)
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{
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wire_stupidity_into_tlb();
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mips_hpt_frequency = cpu_clock / 2;
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board_timer_setup = momenco_timer_setup;
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rtc_get_time = m48t37y_get_time;
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rtc_set_time = m48t37y_set_time;
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}
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static struct resource mv_pci_io_mem0_resource = {
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.name = "MV64340 PCI0 IO MEM",
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.flags = IORESOURCE_IO
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};
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static struct resource mv_pci_mem0_resource = {
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.name = "MV64340 PCI0 MEM",
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.flags = IORESOURCE_MEM
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};
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static struct mv_pci_controller mv_bus0_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = &mv_pci_mem0_resource,
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.io_resource = &mv_pci_io_mem0_resource,
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},
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.config_addr = MV64340_PCI_0_CONFIG_ADDR,
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.config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
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};
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static uint32_t mv_io_base, mv_io_size;
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static void ja_pci0_init(void)
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{
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uint32_t mem0_base, mem0_size;
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uint32_t io_base, io_size;
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io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
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io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
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mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
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mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
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mv_pci_io_mem0_resource.start = 0;
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mv_pci_io_mem0_resource.end = io_size - 1;
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mv_pci_mem0_resource.start = mem0_base;
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mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
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mv_bus0_controller.pcic.mem_offset = mem0_base;
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mv_bus0_controller.pcic.io_offset = 0;
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ioport_resource.end = io_size - 1;
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register_pci_controller(&mv_bus0_controller.pcic);
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mv_io_base = io_base;
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mv_io_size = io_size;
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}
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static struct resource mv_pci_io_mem1_resource = {
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.name = "MV64340 PCI1 IO MEM",
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.flags = IORESOURCE_IO
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};
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static struct resource mv_pci_mem1_resource = {
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.name = "MV64340 PCI1 MEM",
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.flags = IORESOURCE_MEM
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};
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static struct mv_pci_controller mv_bus1_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = &mv_pci_mem1_resource,
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.io_resource = &mv_pci_io_mem1_resource,
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},
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.config_addr = MV64340_PCI_1_CONFIG_ADDR,
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.config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
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};
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static __init void ja_pci1_init(void)
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{
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uint32_t mem0_base, mem0_size;
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uint32_t io_base, io_size;
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io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
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io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
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mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
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mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
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/*
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* Here we assume the I/O window of second bus to be contiguous with
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* the first. A gap is no problem but would waste address space for
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* remapping the port space.
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*/
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mv_pci_io_mem1_resource.start = mv_io_size;
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mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
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mv_pci_mem1_resource.start = mem0_base;
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mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
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mv_bus1_controller.pcic.mem_offset = mem0_base;
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mv_bus1_controller.pcic.io_offset = 0;
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ioport_resource.end = io_base + io_size -mv_io_base - 1;
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register_pci_controller(&mv_bus1_controller.pcic);
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mv_io_size = io_base + io_size - mv_io_base;
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}
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static __init int __init ja_pci_init(void)
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{
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unsigned long io_v_base;
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uint32_t enable;
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enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
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/*
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* We require at least one enabled I/O or PCI memory window or we
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* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
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*/
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if (enable & (0x01 << 9) || enable & (0x01 << 10))
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ja_pci0_init();
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if (enable & (0x01 << 14) || enable & (0x01 << 15))
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ja_pci1_init();
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if (mv_io_size) {
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io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
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if (!io_v_base)
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panic("Could not ioremap I/O port range");
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set_io_port_base(io_v_base);
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}
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return 0;
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}
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arch_initcall(ja_pci_init);
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void __init plat_setup(void)
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{
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unsigned int tmpword;
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board_time_init = momenco_time_init;
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_machine_restart = momenco_jaguar_restart;
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_machine_halt = momenco_jaguar_halt;
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_machine_power_off = momenco_jaguar_power_off;
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/*
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* initrd_start = (ulong)jaguar_initrd_start;
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* initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
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* initrd_below_start_ok = 1;
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*/
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wire_stupidity_into_tlb();
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/*
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* shut down ethernet ports, just to be sure our memory doesn't get
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* corrupted by random ethernet traffic.
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*/
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MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
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MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
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MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
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MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
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MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
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MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
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while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
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while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
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while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
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while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
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while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
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while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
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MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
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MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
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MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
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MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
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MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
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MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
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/* Turn off the Bit-Error LED */
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JAGUAR_FPGA_WRITE(0x80, CLR);
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tmpword = JAGUAR_FPGA_READ(BOARDREV);
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if (tmpword < 26)
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printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
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'A'+tmpword);
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else
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printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
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tmpword);
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tmpword = JAGUAR_FPGA_READ(FPGA_REV);
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printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
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tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
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printk("Reset reason: 0x%x\n", tmpword);
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switch (tmpword) {
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case 0x1:
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printk(" - Power-up reset\n");
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break;
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case 0x2:
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printk(" - Push-button reset\n");
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break;
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case 0x8:
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printk(" - Watchdog reset\n");
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break;
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case 0x10:
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printk(" - JTAG reset\n");
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break;
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default:
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printk(" - Unknown reset cause\n");
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}
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reset_reason = tmpword;
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JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
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tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
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printk("Board Status register: 0x%02x\n", tmpword);
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printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
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printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
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/* 256MiB of RM9000x2 DDR */
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// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
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/* 128MiB of MV-64340 DDR */
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// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
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/* XXX Memory configuration should be picked up from PMON2k */
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#ifdef CONFIG_JAGUAR_DMALOW
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printk("Jaguar ATX DMA-low mode set\n");
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add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
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add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
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#else
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/* 128MiB of MV-64340 DDR RAM */
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printk("Jaguar ATX DMA-low mode is not set\n");
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add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
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#endif
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#ifdef GEMDEBUG_TRACEBUFFER
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{
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unsigned int tbControl;
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tbControl =
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0 << 26 | /* post trigger delay 0 */
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0x2 << 16 | /* sequential trace mode */
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// 0x0 << 16 | /* non-sequential trace mode */
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// 0xf << 4 | /* watchpoints disabled */
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2 << 2 | /* armed */
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2 ; /* interrupt disabled */
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printk ("setting tbControl = %08lx\n", tbControl);
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write_32bit_cp0_set1_register($22, tbControl);
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__asm__ __volatile__(".set noreorder\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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".set reorder\n\t");
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}
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#endif
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}
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