8ce877a8eb
The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
71 lines
2.6 KiB
C
71 lines
2.6 KiB
C
/****************************************************************************/
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/*
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* m53xxacr.h -- ColdFire version 3 core cache support
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*
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* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m53xxacr_h
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#define m53xxacr_h
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/****************************************************************************/
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/*
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* All varients of the ColdFire using version 3 cores have a similar
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* cache setup. They have a unified instruction and data cache, with
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* configurable write-through or copy-back operation.
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*/
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/*
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* Define the Cache Control register flags.
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*/
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#define CACR_EC 0x80000000 /* Enable cache */
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#define CACR_ESB 0x20000000 /* Enable store buffer */
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#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_HLCK 0x08000000 /* Half cache lock mode */
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#define CACR_CINVA 0x01000000 /* Invalidate cache */
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#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
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#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
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#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
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#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
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#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
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#define CACR_WPROTECT 0x00000020 /* Write protect*/
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#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
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/*
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* Define the Access Control register flags.
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*/
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#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
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#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
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#define ACR_ENABLE 0x00008000 /* Enable this ACR */
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#define ACR_USER 0x00000000 /* Allow only user accesses */
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#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
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#define ACR_ANY 0x00004000 /* Allow any access type */
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#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
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#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
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#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
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#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/*
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* Set the cache controller settings we will use. This default in the
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* CACR is cache inhibited, we use the ACR register to set cacheing
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* enabled on the regions we want (eg RAM).
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*/
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#ifdef CONFIG_COLDFIRE_SW_A7
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#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
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#else
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#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
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#endif
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#define CACHE_INIT CACR_CINVA
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#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
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(0x000f0000) + \
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(ACR_ENABLE + ACR_ANY + ACR_CM_CB))
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#define ACR1_MODE 0
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/****************************************************************************/
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#endif /* m53xxsim_h */
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