d490609321
This improves the PLL timings according to the suggestion of the hardware engineers. This results in some outputs being able to sync that weren't able to before. This is part of fixing fd.o bug #17508. Signed-off-by: Ma Ling <ling.ma@intel.com> [anholt: cleaned up a couple of redundant comments] Signed-off-by: Eric Anholt <eric@anholt.net> |
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