5323180db7
The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU
exception in kernel partially") was broken. The commit was to fix
theoretical problem but broke usual case. Revert it for now.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
261 lines
5.2 KiB
ArmAsm
261 lines
5.2 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1994, 1995, 1996, by Andreas Busse
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2000 MIPS Technologies, Inc.
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* written by Carsten Langgaard, carstenl@mips.com
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*/
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#include <asm/asm.h>
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#include <asm/cachectl.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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#include <asm/asmmacro.h>
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/*
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* Offset to the current process status flags, the first 32 bytes of the
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* stack are not used.
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*/
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#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
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/*
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* FPU context is saved iff the process has used it's FPU in the current
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* time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
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* space STATUS register should be 0, so that a process *always* starts its
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* userland with FPU disabled after each context switch.
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*
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* FPU will be enabled as soon as the process accesses FPU again, through
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* do_cpu() trap.
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*/
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/*
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* task_struct *resume(task_struct *prev, task_struct *next,
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* struct thread_info *next_ti)
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*/
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.align 5
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LEAF(resume)
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#ifndef CONFIG_CPU_HAS_LLSC
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sw zero, ll_bit
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#endif
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mfc0 t1, CP0_STATUS
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LONG_S t1, THREAD_STATUS(a0)
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cpu_save_nonscratch a0
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LONG_S ra, THREAD_REG31(a0)
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/*
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* check if we need to save FPU registers
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*/
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PTR_L t3, TASK_THREAD_INFO(a0)
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LONG_L t0, TI_FLAGS(t3)
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li t1, _TIF_USEDFPU
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and t2, t0, t1
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beqz t2, 1f
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nor t1, zero, t1
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and t0, t0, t1
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LONG_S t0, TI_FLAGS(t3)
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/*
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* clear saved user stack CU1 bit
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*/
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LONG_L t0, ST_OFF(t3)
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li t1, ~ST0_CU1
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and t0, t0, t1
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LONG_S t0, ST_OFF(t3)
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fpu_save_double a0 t0 t1 # c0_status passed in t0
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# clobbers t1
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1:
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/*
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* The order of restoring the registers takes care of the race
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* updating $28, $29 and kernelsp without disabling ints.
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*/
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move $28, a2
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cpu_restore_nonscratch a1
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#if (_THREAD_SIZE - 32) < 0x10000
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PTR_ADDIU t0, $28, _THREAD_SIZE - 32
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#else
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PTR_LI t0, _THREAD_SIZE - 32
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PTR_ADDU t0, $28
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#endif
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set_saved_sp t0, t1, t2
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Read-modify-writes of Status must be atomic on a VPE */
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mfc0 t2, CP0_TCSTATUS
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ori t1, t2, TCSTATUS_IXMT
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mtc0 t1, CP0_TCSTATUS
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andi t2, t2, TCSTATUS_IXMT
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_ehb
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DMT 8 # dmt t0
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move t1,ra
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jal mips_ihb
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move ra,t1
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 t1, CP0_STATUS /* Do we really need this? */
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li a3, 0xff01
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and t1, a3
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LONG_L a2, THREAD_STATUS(a1)
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nor a3, $0, a3
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and a2, a3
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or a2, t1
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mtc0 a2, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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_ehb
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andi t0, t0, VPECONTROL_TE
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beqz t0, 1f
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emt
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1:
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mfc0 t1, CP0_TCSTATUS
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xori t1, t1, TCSTATUS_IXMT
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or t1, t1, t2
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mtc0 t1, CP0_TCSTATUS
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_ehb
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#endif /* CONFIG_MIPS_MT_SMTC */
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move v0, a0
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jr ra
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END(resume)
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/*
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* Save a thread's fp context.
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*/
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LEAF(_save_fp)
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#ifdef CONFIG_64BIT
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mfc0 t0, CP0_STATUS
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#endif
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fpu_save_double a0 t0 t1 # clobbers t1
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jr ra
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END(_save_fp)
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/*
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* Restore a thread's fp context.
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*/
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LEAF(_restore_fp)
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#ifdef CONFIG_64BIT
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mfc0 t0, CP0_STATUS
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#endif
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fpu_restore_double a0 t0 t1 # clobbers t1
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jr ra
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END(_restore_fp)
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using has
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* the property that no matter whether considered as single or as double
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* precision represents signaling NANS.
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*
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* We initialize fcr31 to rounding to nearest, no exceptions.
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*/
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#define FPU_DEFAULT 0x00000000
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LEAF(_init_fpu)
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
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mfc0 t0, CP0_TCSTATUS
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/* Bit position is the same for Status, TCStatus */
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_TCSTATUS
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#else /* Normal MIPS CU1 enable */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_STATUS
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#endif /* CONFIG_MIPS_MT_SMTC */
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fpu_enable_hazard
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li t1, FPU_DEFAULT
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ctc1 t1, fcr31
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li t1, -1 # SNaN
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#ifdef CONFIG_64BIT
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sll t0, t0, 5
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bgez t0, 1f # 16 / 32 register mode?
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dmtc1 t1, $f1
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dmtc1 t1, $f3
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dmtc1 t1, $f5
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dmtc1 t1, $f7
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dmtc1 t1, $f9
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dmtc1 t1, $f11
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dmtc1 t1, $f13
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dmtc1 t1, $f15
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dmtc1 t1, $f17
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dmtc1 t1, $f19
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dmtc1 t1, $f21
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dmtc1 t1, $f23
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dmtc1 t1, $f25
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dmtc1 t1, $f27
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dmtc1 t1, $f29
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dmtc1 t1, $f31
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1:
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#endif
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#ifdef CONFIG_CPU_MIPS32
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mtc1 t1, $f0
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mtc1 t1, $f1
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mtc1 t1, $f2
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mtc1 t1, $f3
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mtc1 t1, $f4
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mtc1 t1, $f5
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mtc1 t1, $f6
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mtc1 t1, $f7
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mtc1 t1, $f8
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mtc1 t1, $f9
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mtc1 t1, $f10
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mtc1 t1, $f11
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mtc1 t1, $f12
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mtc1 t1, $f13
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mtc1 t1, $f14
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mtc1 t1, $f15
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mtc1 t1, $f16
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mtc1 t1, $f17
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mtc1 t1, $f18
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mtc1 t1, $f19
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mtc1 t1, $f20
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mtc1 t1, $f21
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mtc1 t1, $f22
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mtc1 t1, $f23
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mtc1 t1, $f24
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mtc1 t1, $f25
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mtc1 t1, $f26
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mtc1 t1, $f27
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mtc1 t1, $f28
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mtc1 t1, $f29
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mtc1 t1, $f30
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mtc1 t1, $f31
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#else
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.set mips3
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dmtc1 t1, $f0
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dmtc1 t1, $f2
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dmtc1 t1, $f4
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dmtc1 t1, $f6
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dmtc1 t1, $f8
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dmtc1 t1, $f10
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dmtc1 t1, $f12
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dmtc1 t1, $f14
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dmtc1 t1, $f16
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dmtc1 t1, $f18
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dmtc1 t1, $f20
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dmtc1 t1, $f22
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dmtc1 t1, $f24
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dmtc1 t1, $f26
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dmtc1 t1, $f28
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dmtc1 t1, $f30
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#endif
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jr ra
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END(_init_fpu)
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