54293ec307
Here we define the addresses and bit-fields of the Configuration and
Status Registers (CSRs) for some of the hardware functional units on
the OCTEON SOC.
Definitions are needed for:
CIU -- Central Interrupt Unit.
GPIO -- General Purpose Input Output.
IOB -- Input / Output {Busing,Bridge}.
IPD -- Input Packet Data unit.
L2C -- Level-2 Cache controller.
L2D -- Level-2 Data cache.
L2T -- Level-2 cache Tag.
LED -- Light Emitting Diode controller.
MIO -- Miscellaneous Input / Output.
POW -- Packet Order / Work unit.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_L2T_DEFS_H__
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#define __CVMX_L2T_DEFS_H__
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#define CVMX_L2T_ERR \
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CVMX_ADD_IO_SEG(0x0001180080000008ull)
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union cvmx_l2t_err {
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uint64_t u64;
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struct cvmx_l2t_err_s {
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uint64_t reserved_29_63:35;
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uint64_t fadru:1;
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uint64_t lck_intena2:1;
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uint64_t lckerr2:1;
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uint64_t lck_intena:1;
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uint64_t lckerr:1;
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uint64_t fset:3;
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uint64_t fadr:10;
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uint64_t fsyn:6;
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uint64_t ded_err:1;
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uint64_t sec_err:1;
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uint64_t ded_intena:1;
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uint64_t sec_intena:1;
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uint64_t ecc_ena:1;
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} s;
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struct cvmx_l2t_err_cn30xx {
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uint64_t reserved_28_63:36;
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uint64_t lck_intena2:1;
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uint64_t lckerr2:1;
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uint64_t lck_intena:1;
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uint64_t lckerr:1;
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uint64_t reserved_23_23:1;
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uint64_t fset:2;
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uint64_t reserved_19_20:2;
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uint64_t fadr:8;
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uint64_t fsyn:6;
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uint64_t ded_err:1;
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uint64_t sec_err:1;
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uint64_t ded_intena:1;
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uint64_t sec_intena:1;
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uint64_t ecc_ena:1;
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} cn30xx;
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struct cvmx_l2t_err_cn31xx {
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uint64_t reserved_28_63:36;
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uint64_t lck_intena2:1;
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uint64_t lckerr2:1;
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uint64_t lck_intena:1;
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uint64_t lckerr:1;
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uint64_t reserved_23_23:1;
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uint64_t fset:2;
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uint64_t reserved_20_20:1;
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uint64_t fadr:9;
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uint64_t fsyn:6;
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uint64_t ded_err:1;
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uint64_t sec_err:1;
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uint64_t ded_intena:1;
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uint64_t sec_intena:1;
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uint64_t ecc_ena:1;
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} cn31xx;
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struct cvmx_l2t_err_cn38xx {
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uint64_t reserved_28_63:36;
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uint64_t lck_intena2:1;
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uint64_t lckerr2:1;
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uint64_t lck_intena:1;
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uint64_t lckerr:1;
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uint64_t fset:3;
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uint64_t fadr:10;
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uint64_t fsyn:6;
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uint64_t ded_err:1;
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uint64_t sec_err:1;
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uint64_t ded_intena:1;
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uint64_t sec_intena:1;
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uint64_t ecc_ena:1;
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} cn38xx;
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struct cvmx_l2t_err_cn38xx cn38xxp2;
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struct cvmx_l2t_err_cn50xx {
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uint64_t reserved_28_63:36;
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uint64_t lck_intena2:1;
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uint64_t lckerr2:1;
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uint64_t lck_intena:1;
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uint64_t lckerr:1;
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uint64_t fset:3;
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uint64_t reserved_18_20:3;
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uint64_t fadr:7;
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uint64_t fsyn:6;
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uint64_t ded_err:1;
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uint64_t sec_err:1;
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uint64_t ded_intena:1;
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uint64_t sec_intena:1;
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uint64_t ecc_ena:1;
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} cn50xx;
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struct cvmx_l2t_err_cn52xx {
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uint64_t reserved_28_63:36;
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uint64_t lck_intena2:1;
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uint64_t lckerr2:1;
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uint64_t lck_intena:1;
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uint64_t lckerr:1;
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uint64_t fset:3;
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uint64_t reserved_20_20:1;
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uint64_t fadr:9;
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uint64_t fsyn:6;
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uint64_t ded_err:1;
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uint64_t sec_err:1;
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uint64_t ded_intena:1;
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uint64_t sec_intena:1;
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uint64_t ecc_ena:1;
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} cn52xx;
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struct cvmx_l2t_err_cn52xx cn52xxp1;
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struct cvmx_l2t_err_s cn56xx;
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struct cvmx_l2t_err_s cn56xxp1;
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struct cvmx_l2t_err_s cn58xx;
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struct cvmx_l2t_err_s cn58xxp1;
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};
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#endif
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