sheenam monga d87a3b89cb qcacld-3.0: Handle bus bandwidth in start and stop modules ... Currently, bus bandwidth is initialized and deinitialized in different memory domains which may cause leaks due to async bandwidth init and deinit. Fix is to initialize and de-initialize bus bandwidth in active domain. Change-Id: I67cf9ecdd47c8f3ca6e9b272ca379f0cac9a6c7b CRs-Fixed: 2568881		2019-12-21 12:15:05 -08:00
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bmi	qcacld-3.0: Add synchronization between unloading & SSR recovering	2019-10-19 19:25:31 -07:00
cds	qcacld-3.0: Add 80211 BAR frame	2019-12-13 20:39:05 -08:00
dp	qcacld-3.0: Clean up channel number usage for CDP API	2019-12-16 19:45:14 -08:00
hdd	qcacld-3.0: Handle bus bandwidth in start and stop modules	2019-12-21 12:15:05 -08:00
mac	Release 5.2.0.162E	2019-12-20 20:05:56 -08:00
pld	qcacld-3.0: Don't set unload flags before unregister_driver when unloading	2019-12-20 20:05:56 -08:00
sap	qcacld-3.0: 5G SAP failed to channel switch for sta connecting	2019-12-20 03:51:51 -08:00
sme	qcacld-3.0: Add support for oem data event	2019-12-17 14:09:53 -08:00
wma	qcacld-3.0: Send max AMSDU size to firmware	2019-12-19 07:09:32 -08:00