edb6310aaa
The following patch add support for the NXP PNX833x SOC. More specifically it adds support for the STB222/5 variant. It fixes the vectored interrupt issue. Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* irq.h: IRQ mappings for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
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#define __ASM_MIPS_MACH_PNX833X_IRQ_H
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/*
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* The "IRQ numbers" are completely virtual.
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*
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* In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48.
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* Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt,
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* numbers 49..64 for (virtual) GPIO interrupts.
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*
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* In PNX8335, we have 57 interrupt lines, numbered from 1 to 57,
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* connected to PIC, which uses core hardware interrupt 2, and also
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* a timer interrupt through hardware interrupt 5.
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* Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt,
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* numbers 65..80 for (virtual) GPIO interrupts.
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*
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*/
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#if defined(CONFIG_SOC_PNX8335)
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#define PNX833X_PIC_NUM_IRQ 58
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#else
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#define PNX833X_PIC_NUM_IRQ 37
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#endif
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#define MIPS_CPU_NUM_IRQ 8
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#define PNX833X_GPIO_NUM_IRQ 16
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#define MIPS_CPU_IRQ_BASE 0
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#define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
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#define PNX833X_GPIO_IRQ_BASE (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ)
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#define NR_IRQS (MIPS_CPU_NUM_IRQ + PNX833X_PIC_NUM_IRQ + PNX833X_GPIO_NUM_IRQ)
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#endif
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