d8caf74f1b
Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
227 lines
5.6 KiB
C
227 lines
5.6 KiB
C
/*
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* Celleb setup code
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*
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* (C) Copyright 2006-2007 TOSHIBA CORPORATION
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*
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* This code is based on arch/powerpc/platforms/cell/setup.c:
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* Modified by PPC64 Team, IBM Corp
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* Modified by Cell Team, IBM Deutschland Entwicklung GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#undef DEBUG
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/console.h>
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#include <linux/of_platform.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/kexec.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/cputable.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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#include <asm/spu_priv1.h>
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#include <asm/firmware.h>
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#include <asm/rtas.h>
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#include <asm/cell-regs.h>
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#include "interrupt.h"
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#include "beat_wrapper.h"
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#include "beat.h"
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#include "pci.h"
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#include "../cell/interrupt.h"
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#include "../cell/pervasive.h"
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#include "../cell/ras.h"
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static char celleb_machine_type[128] = "Celleb";
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static void celleb_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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/* using "CHRP" is to trick anaconda into installing FCx into Celleb */
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seq_printf(m, "machine\t\t: %s %s\n", celleb_machine_type, model);
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of_node_put(root);
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}
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static int __init celleb_machine_type_hack(char *ptr)
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{
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strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
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celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
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return 0;
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}
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__setup("celleb_machine_type_hack=", celleb_machine_type_hack);
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static void celleb_progress(char *s, unsigned short hex)
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{
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printk("*** %04x : %s\n", hex, s ? s : "");
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}
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static void __init celleb_init_IRQ_native(void)
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{
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iic_init_IRQ();
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spider_init_IRQ();
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}
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static void __init celleb_setup_arch_beat(void)
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{
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ppc_md.restart = beat_restart;
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ppc_md.power_off = beat_power_off;
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ppc_md.halt = beat_halt;
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ppc_md.get_rtc_time = beat_get_rtc_time;
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ppc_md.set_rtc_time = beat_set_rtc_time;
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ppc_md.power_save = beat_power_save;
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ppc_md.nvram_size = beat_nvram_get_size;
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ppc_md.nvram_read = beat_nvram_read;
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ppc_md.nvram_write = beat_nvram_write;
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ppc_md.set_dabr = beat_set_xdabr;
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ppc_md.init_IRQ = beatic_init_IRQ;
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ppc_md.get_irq = beatic_get_irq;
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#ifdef CONFIG_KEXEC
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ppc_md.kexec_cpu_down = beat_kexec_cpu_down;
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#endif
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_beat_ops;
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spu_management_ops = &spu_management_of_ops;
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#endif
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#ifdef CONFIG_SMP
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smp_init_celleb();
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#endif
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}
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static void __init celleb_setup_arch_native(void)
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{
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ppc_md.restart = rtas_restart;
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ppc_md.power_off = rtas_power_off;
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ppc_md.halt = rtas_halt;
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ppc_md.get_boot_time = rtas_get_boot_time;
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ppc_md.get_rtc_time = rtas_get_rtc_time;
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ppc_md.set_rtc_time = rtas_set_rtc_time;
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ppc_md.init_IRQ = celleb_init_IRQ_native;
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#ifdef CONFIG_SPU_BASE
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spu_priv1_ops = &spu_priv1_mmio_ops;
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spu_management_ops = &spu_management_of_ops;
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#endif
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cbe_regs_init();
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#ifdef CONFIG_CBE_RAS
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cbe_ras_init();
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#endif
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#ifdef CONFIG_SMP
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smp_init_cell();
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#endif
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cbe_pervasive_init();
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}
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static void __init celleb_setup_arch(void)
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{
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if (firmware_has_feature(FW_FEATURE_BEAT))
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celleb_setup_arch_beat();
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else
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celleb_setup_arch_native();
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000;
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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}
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static int __init celleb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "Beat")) {
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powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS
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| FW_FEATURE_BEAT | FW_FEATURE_LPAR;
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hpte_init_beat_v3();
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return 1;
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}
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if (of_flat_dt_is_compatible(root, "TOSHIBA,Celleb")) {
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powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
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hpte_init_native();
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return 1;
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}
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return 0;
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}
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static struct of_device_id celleb_bus_ids[] __initdata = {
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{ .type = "scc", },
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{ .type = "ioif", }, /* old style */
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{},
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};
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static int __init celleb_publish_devices(void)
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{
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if (!machine_is(celleb))
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return 0;
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/* Publish OF platform devices for southbridge IOs */
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of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
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celleb_pci_workaround_init();
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return 0;
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}
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device_initcall(celleb_publish_devices);
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define_machine(celleb) {
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.name = "Cell Reference Set",
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.probe = celleb_probe,
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.setup_arch = celleb_setup_arch,
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.show_cpuinfo = celleb_show_cpuinfo,
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.calibrate_decr = generic_calibrate_decr,
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.progress = celleb_progress,
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.pci_probe_mode = celleb_pci_probe_mode,
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.pci_setup_phb = celleb_setup_phb,
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#ifdef CONFIG_KEXEC
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.machine_kexec = default_machine_kexec,
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.machine_kexec_prepare = default_machine_kexec_prepare,
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.machine_crash_shutdown = default_machine_crash_shutdown,
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#endif
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};
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