12b8eb8652
This allows us to determine the irq controller base address on runtime. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
156 lines
4.5 KiB
C
156 lines
4.5 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#define AVIC_INTCNTL 0x00 /* int control reg */
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#define AVIC_NIMASK 0x04 /* int mask reg */
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#define AVIC_INTENNUM 0x08 /* int enable number reg */
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#define AVIC_INTDISNUM 0x0C /* int disable number reg */
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#define AVIC_INTENABLEH 0x10 /* int enable reg high */
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#define AVIC_INTENABLEL 0x14 /* int enable reg low */
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#define AVIC_INTTYPEH 0x18 /* int type reg high */
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#define AVIC_INTTYPEL 0x1C /* int type reg low */
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#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
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#define AVIC_NIVECSR 0x40 /* norm int vector/status */
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#define AVIC_FIVECSR 0x44 /* fast int vector/status */
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#define AVIC_INTSRCH 0x48 /* int source reg high */
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#define AVIC_INTSRCL 0x4C /* int source reg low */
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#define AVIC_INTFRCH 0x50 /* int force reg high */
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#define AVIC_INTFRCL 0x54 /* int force reg low */
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#define AVIC_NIPNDH 0x58 /* norm int pending high */
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#define AVIC_NIPNDL 0x5C /* norm int pending low */
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#define AVIC_FIPNDH 0x60 /* fast int pending high */
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#define AVIC_FIPNDL 0x64 /* fast int pending low */
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void __iomem *avic_base;
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int imx_irq_set_priority(unsigned char irq, unsigned char prio)
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{
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#ifdef CONFIG_MXC_IRQ_PRIOR
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unsigned int temp;
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unsigned int mask = 0x0F << irq % 8 * 4;
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if (irq >= MXC_INTERNAL_IRQS)
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return -EINVAL;;
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temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
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temp &= ~mask;
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temp |= prio & mask;
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__raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
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return 0;
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#else
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return -ENOSYS;
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#endif
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}
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EXPORT_SYMBOL(imx_irq_set_priority);
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#ifdef CONFIG_FIQ
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int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
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{
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unsigned int irqt;
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if (irq >= MXC_INTERNAL_IRQS)
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return -EINVAL;
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if (irq < MXC_INTERNAL_IRQS / 2) {
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irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
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__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
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} else {
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irq -= MXC_INTERNAL_IRQS / 2;
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irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
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__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
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}
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return 0;
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}
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EXPORT_SYMBOL(mxc_set_irq_fiq);
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#endif /* CONFIG_FIQ */
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/* Disable interrupt number "irq" in the AVIC */
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static void mxc_mask_irq(unsigned int irq)
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{
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__raw_writel(irq, avic_base + AVIC_INTDISNUM);
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}
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/* Enable interrupt number "irq" in the AVIC */
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static void mxc_unmask_irq(unsigned int irq)
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{
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__raw_writel(irq, avic_base + AVIC_INTENNUM);
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}
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static struct irq_chip mxc_avic_chip = {
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.ack = mxc_mask_irq,
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.mask = mxc_mask_irq,
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.unmask = mxc_unmask_irq,
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};
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/*
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* This function initializes the AVIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* to the kernel for each interrupt source.
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*/
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void __init mxc_init_irq(void __iomem *irqbase)
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{
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int i;
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avic_base = irqbase;
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/* put the AVIC into the reset value with
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* all interrupts disabled
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*/
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__raw_writel(0, avic_base + AVIC_INTCNTL);
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__raw_writel(0x1f, avic_base + AVIC_NIMASK);
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/* disable all interrupts */
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__raw_writel(0, avic_base + AVIC_INTENABLEH);
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__raw_writel(0, avic_base + AVIC_INTENABLEL);
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/* all IRQ no FIQ */
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__raw_writel(0, avic_base + AVIC_INTTYPEH);
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__raw_writel(0, avic_base + AVIC_INTTYPEL);
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for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
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set_irq_chip(i, &mxc_avic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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/* Set default priority value (0) for all IRQ's */
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for (i = 0; i < 8; i++)
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__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
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/* init architectures chained interrupt handler */
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mxc_register_gpios();
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#ifdef CONFIG_FIQ
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/* Initialize FIQ */
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init_FIQ();
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#endif
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printk(KERN_INFO "MXC IRQ initialized\n");
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}
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