59fef3b1e9
The driver allocates SRQ WQEs size with a power of 2 size both for Tavor and for memfree. For Tavor, however, the hardware only requires the WQE size to be a multiple of 16, not a power of 2, and the max number of scatter-gather allowed is reported accordingly by the firmware (and this is the value currently returned by ib_query_device() and ibv_query_device()). If the max number of scatter/gather entries reported by the FW is used when creating an SRQ, the creation will fail for Tavor, since the required WQE size will be increased to the next power of 2, which turns out to be larger than the device permitted max WQE size (which is not a power of 2). This patch reduces the reported SRQ max wqe size so that it can be used successfully in creating an SRQ on Tavor HCAs. Signed-off-by: Jack Morgenstein <jackm@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
589 lines
18 KiB
C
589 lines
18 KiB
C
/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
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* Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
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*/
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#ifndef MTHCA_DEV_H
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#define MTHCA_DEV_H
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#include <linux/spinlock.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/timer.h>
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#include <linux/mutex.h>
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#include <asm/semaphore.h>
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#include "mthca_provider.h"
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#include "mthca_doorbell.h"
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#define DRV_NAME "ib_mthca"
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#define PFX DRV_NAME ": "
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#define DRV_VERSION "0.08"
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#define DRV_RELDATE "February 14, 2006"
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enum {
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MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
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MTHCA_FLAG_SRQ = 1 << 2,
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MTHCA_FLAG_MSI = 1 << 3,
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MTHCA_FLAG_MSI_X = 1 << 4,
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MTHCA_FLAG_NO_LAM = 1 << 5,
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MTHCA_FLAG_FMR = 1 << 6,
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MTHCA_FLAG_MEMFREE = 1 << 7,
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MTHCA_FLAG_PCIE = 1 << 8,
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MTHCA_FLAG_SINAI_OPT = 1 << 9
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};
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enum {
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MTHCA_MAX_PORTS = 2
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};
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enum {
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MTHCA_BOARD_ID_LEN = 64
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};
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enum {
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MTHCA_EQ_CONTEXT_SIZE = 0x40,
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MTHCA_CQ_CONTEXT_SIZE = 0x40,
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MTHCA_QP_CONTEXT_SIZE = 0x200,
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MTHCA_RDB_ENTRY_SIZE = 0x20,
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MTHCA_AV_SIZE = 0x20,
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MTHCA_MGM_ENTRY_SIZE = 0x40,
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/* Arbel FW gives us these, but we need them for Tavor */
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MTHCA_MPT_ENTRY_SIZE = 0x40,
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MTHCA_MTT_SEG_SIZE = 0x40,
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MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
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};
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enum {
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MTHCA_EQ_CMD,
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MTHCA_EQ_ASYNC,
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MTHCA_EQ_COMP,
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MTHCA_NUM_EQ
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};
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enum {
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MTHCA_OPCODE_NOP = 0x00,
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MTHCA_OPCODE_RDMA_WRITE = 0x08,
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MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
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MTHCA_OPCODE_SEND = 0x0a,
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MTHCA_OPCODE_SEND_IMM = 0x0b,
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MTHCA_OPCODE_RDMA_READ = 0x10,
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MTHCA_OPCODE_ATOMIC_CS = 0x11,
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MTHCA_OPCODE_ATOMIC_FA = 0x12,
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MTHCA_OPCODE_BIND_MW = 0x18,
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MTHCA_OPCODE_INVALID = 0xff
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};
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enum {
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MTHCA_CMD_USE_EVENTS = 1 << 0,
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MTHCA_CMD_POST_DOORBELLS = 1 << 1
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};
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enum {
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MTHCA_CMD_NUM_DBELL_DWORDS = 8
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};
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struct mthca_cmd {
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struct pci_pool *pool;
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struct mutex hcr_mutex;
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struct semaphore poll_sem;
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struct semaphore event_sem;
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int max_cmds;
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spinlock_t context_lock;
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int free_head;
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struct mthca_cmd_context *context;
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u16 token_mask;
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u32 flags;
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void __iomem *dbell_map;
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u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
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};
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struct mthca_limits {
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int num_ports;
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int vl_cap;
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int mtu_cap;
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int gid_table_len;
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int pkey_table_len;
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int local_ca_ack_delay;
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int num_uars;
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int max_sg;
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int num_qps;
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int max_wqes;
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int max_desc_sz;
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int max_qp_init_rdma;
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int reserved_qps;
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int num_srqs;
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int max_srq_wqes;
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int max_srq_sge;
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int reserved_srqs;
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int num_eecs;
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int reserved_eecs;
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int num_cqs;
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int max_cqes;
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int reserved_cqs;
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int num_eqs;
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int reserved_eqs;
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int num_mpts;
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int num_mtt_segs;
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int fmr_reserved_mtts;
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int reserved_mtts;
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int reserved_mrws;
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int reserved_uars;
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int num_mgms;
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int num_amgms;
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int reserved_mcgs;
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int num_pds;
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int reserved_pds;
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u32 page_size_cap;
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u32 flags;
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u16 stat_rate_support;
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u8 port_width_cap;
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};
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struct mthca_alloc {
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u32 last;
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u32 top;
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u32 max;
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u32 mask;
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spinlock_t lock;
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unsigned long *table;
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};
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struct mthca_array {
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struct {
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void **page;
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int used;
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} *page_list;
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};
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struct mthca_uar_table {
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struct mthca_alloc alloc;
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u64 uarc_base;
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int uarc_size;
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};
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struct mthca_pd_table {
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struct mthca_alloc alloc;
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};
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struct mthca_buddy {
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unsigned long **bits;
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int max_order;
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spinlock_t lock;
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};
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struct mthca_mr_table {
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struct mthca_alloc mpt_alloc;
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struct mthca_buddy mtt_buddy;
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struct mthca_buddy *fmr_mtt_buddy;
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u64 mtt_base;
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u64 mpt_base;
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struct mthca_icm_table *mtt_table;
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struct mthca_icm_table *mpt_table;
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struct {
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void __iomem *mpt_base;
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void __iomem *mtt_base;
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struct mthca_buddy mtt_buddy;
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} tavor_fmr;
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};
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struct mthca_eq_table {
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struct mthca_alloc alloc;
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void __iomem *clr_int;
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u32 clr_mask;
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u32 arm_mask;
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struct mthca_eq eq[MTHCA_NUM_EQ];
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u64 icm_virt;
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struct page *icm_page;
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dma_addr_t icm_dma;
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int have_irq;
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u8 inta_pin;
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};
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struct mthca_cq_table {
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struct mthca_alloc alloc;
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spinlock_t lock;
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struct mthca_array cq;
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struct mthca_icm_table *table;
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};
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struct mthca_srq_table {
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struct mthca_alloc alloc;
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spinlock_t lock;
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struct mthca_array srq;
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struct mthca_icm_table *table;
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};
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struct mthca_qp_table {
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struct mthca_alloc alloc;
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u32 rdb_base;
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int rdb_shift;
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int sqp_start;
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spinlock_t lock;
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struct mthca_array qp;
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struct mthca_icm_table *qp_table;
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struct mthca_icm_table *eqp_table;
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struct mthca_icm_table *rdb_table;
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};
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struct mthca_av_table {
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struct pci_pool *pool;
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int num_ddr_avs;
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u64 ddr_av_base;
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void __iomem *av_map;
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struct mthca_alloc alloc;
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};
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struct mthca_mcg_table {
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struct mutex mutex;
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struct mthca_alloc alloc;
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struct mthca_icm_table *table;
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};
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struct mthca_catas_err {
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u64 addr;
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u32 __iomem *map;
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unsigned long stop;
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u32 size;
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struct timer_list timer;
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};
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struct mthca_dev {
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struct ib_device ib_dev;
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struct pci_dev *pdev;
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int hca_type;
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unsigned long mthca_flags;
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unsigned long device_cap_flags;
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u32 rev_id;
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char board_id[MTHCA_BOARD_ID_LEN];
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/* firmware info */
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u64 fw_ver;
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union {
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struct {
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u64 fw_start;
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u64 fw_end;
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} tavor;
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struct {
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u64 clr_int_base;
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u64 eq_arm_base;
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u64 eq_set_ci_base;
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struct mthca_icm *fw_icm;
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struct mthca_icm *aux_icm;
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u16 fw_pages;
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} arbel;
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} fw;
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u64 ddr_start;
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u64 ddr_end;
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MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
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struct mutex cap_mask_mutex;
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void __iomem *hcr;
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void __iomem *kar;
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void __iomem *clr_base;
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union {
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struct {
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void __iomem *ecr_base;
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} tavor;
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struct {
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void __iomem *eq_arm;
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void __iomem *eq_set_ci_base;
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} arbel;
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} eq_regs;
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struct mthca_cmd cmd;
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struct mthca_limits limits;
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struct mthca_uar_table uar_table;
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struct mthca_pd_table pd_table;
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struct mthca_mr_table mr_table;
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struct mthca_eq_table eq_table;
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struct mthca_cq_table cq_table;
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struct mthca_srq_table srq_table;
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struct mthca_qp_table qp_table;
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struct mthca_av_table av_table;
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struct mthca_mcg_table mcg_table;
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struct mthca_catas_err catas_err;
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struct mthca_uar driver_uar;
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struct mthca_db_table *db_tab;
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struct mthca_pd driver_pd;
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struct mthca_mr driver_mr;
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struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
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struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
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spinlock_t sm_lock;
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u8 rate[MTHCA_MAX_PORTS];
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};
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#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
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extern int mthca_debug_level;
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#define mthca_dbg(mdev, format, arg...) \
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do { \
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if (mthca_debug_level) \
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dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
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} while (0)
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#else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
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#define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
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#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
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#define mthca_err(mdev, format, arg...) \
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dev_err(&mdev->pdev->dev, format, ## arg)
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#define mthca_info(mdev, format, arg...) \
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dev_info(&mdev->pdev->dev, format, ## arg)
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#define mthca_warn(mdev, format, arg...) \
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dev_warn(&mdev->pdev->dev, format, ## arg)
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extern void __buggy_use_of_MTHCA_GET(void);
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extern void __buggy_use_of_MTHCA_PUT(void);
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#define MTHCA_GET(dest, source, offset) \
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do { \
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void *__p = (char *) (source) + (offset); \
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switch (sizeof (dest)) { \
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case 1: (dest) = *(u8 *) __p; break; \
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case 2: (dest) = be16_to_cpup(__p); break; \
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case 4: (dest) = be32_to_cpup(__p); break; \
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case 8: (dest) = be64_to_cpup(__p); break; \
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default: __buggy_use_of_MTHCA_GET(); \
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} \
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} while (0)
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#define MTHCA_PUT(dest, source, offset) \
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do { \
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void *__d = ((char *) (dest) + (offset)); \
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switch (sizeof(source)) { \
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case 1: *(u8 *) __d = (source); break; \
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case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
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case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
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case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
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default: __buggy_use_of_MTHCA_PUT(); \
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} \
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} while (0)
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int mthca_reset(struct mthca_dev *mdev);
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u32 mthca_alloc(struct mthca_alloc *alloc);
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void mthca_free(struct mthca_alloc *alloc, u32 obj);
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int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
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u32 reserved);
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void mthca_alloc_cleanup(struct mthca_alloc *alloc);
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void *mthca_array_get(struct mthca_array *array, int index);
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int mthca_array_set(struct mthca_array *array, int index, void *value);
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void mthca_array_clear(struct mthca_array *array, int index);
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int mthca_array_init(struct mthca_array *array, int nent);
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void mthca_array_cleanup(struct mthca_array *array, int nent);
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int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
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union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
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int hca_write, struct mthca_mr *mr);
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void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
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int is_direct, struct mthca_mr *mr);
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int mthca_init_uar_table(struct mthca_dev *dev);
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int mthca_init_pd_table(struct mthca_dev *dev);
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int mthca_init_mr_table(struct mthca_dev *dev);
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int mthca_init_eq_table(struct mthca_dev *dev);
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int mthca_init_cq_table(struct mthca_dev *dev);
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int mthca_init_srq_table(struct mthca_dev *dev);
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int mthca_init_qp_table(struct mthca_dev *dev);
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int mthca_init_av_table(struct mthca_dev *dev);
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int mthca_init_mcg_table(struct mthca_dev *dev);
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void mthca_cleanup_uar_table(struct mthca_dev *dev);
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void mthca_cleanup_pd_table(struct mthca_dev *dev);
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void mthca_cleanup_mr_table(struct mthca_dev *dev);
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void mthca_cleanup_eq_table(struct mthca_dev *dev);
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void mthca_cleanup_cq_table(struct mthca_dev *dev);
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void mthca_cleanup_srq_table(struct mthca_dev *dev);
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void mthca_cleanup_qp_table(struct mthca_dev *dev);
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void mthca_cleanup_av_table(struct mthca_dev *dev);
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void mthca_cleanup_mcg_table(struct mthca_dev *dev);
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int mthca_register_device(struct mthca_dev *dev);
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void mthca_unregister_device(struct mthca_dev *dev);
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void mthca_start_catas_poll(struct mthca_dev *dev);
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void mthca_stop_catas_poll(struct mthca_dev *dev);
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int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
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void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
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int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
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void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
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struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
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void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
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int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
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int start_index, u64 *buffer_list, int list_len);
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int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
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u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
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int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
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u32 access, struct mthca_mr *mr);
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int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
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u64 *buffer_list, int buffer_size_shift,
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int list_len, u64 iova, u64 total_size,
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u32 access, struct mthca_mr *mr);
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void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
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int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
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u32 access, struct mthca_fmr *fmr);
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int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
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int list_len, u64 iova);
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void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
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int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
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int list_len, u64 iova);
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void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
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int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
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int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
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void mthca_unmap_eq_icm(struct mthca_dev *dev);
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int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
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struct ib_wc *entry);
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int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
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int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
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int mthca_init_cq(struct mthca_dev *dev, int nent,
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struct mthca_ucontext *ctx, u32 pdn,
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struct mthca_cq *cq);
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void mthca_free_cq(struct mthca_dev *dev,
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struct mthca_cq *cq);
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void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
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void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
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enum ib_event_type event_type);
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void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
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struct mthca_srq *srq);
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void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
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int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
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void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);
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int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
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struct ib_srq_attr *attr, struct mthca_srq *srq);
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void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
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int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
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enum ib_srq_attr_mask attr_mask);
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int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
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int mthca_max_srq_sge(struct mthca_dev *dev);
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void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
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enum ib_event_type event_type);
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void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
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int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
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struct ib_recv_wr **bad_wr);
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int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
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struct ib_recv_wr **bad_wr);
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void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
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enum ib_event_type event_type);
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int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
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struct ib_qp_init_attr *qp_init_attr);
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int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
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int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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struct ib_send_wr **bad_wr);
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int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
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|
struct ib_recv_wr **bad_wr);
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int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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|
struct ib_send_wr **bad_wr);
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int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
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|
struct ib_recv_wr **bad_wr);
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void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
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int index, int *dbd, __be32 *new_wqe);
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int mthca_alloc_qp(struct mthca_dev *dev,
|
|
struct mthca_pd *pd,
|
|
struct mthca_cq *send_cq,
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|
struct mthca_cq *recv_cq,
|
|
enum ib_qp_type type,
|
|
enum ib_sig_type send_policy,
|
|
struct ib_qp_cap *cap,
|
|
struct mthca_qp *qp);
|
|
int mthca_alloc_sqp(struct mthca_dev *dev,
|
|
struct mthca_pd *pd,
|
|
struct mthca_cq *send_cq,
|
|
struct mthca_cq *recv_cq,
|
|
enum ib_sig_type send_policy,
|
|
struct ib_qp_cap *cap,
|
|
int qpn,
|
|
int port,
|
|
struct mthca_sqp *sqp);
|
|
void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
|
|
int mthca_create_ah(struct mthca_dev *dev,
|
|
struct mthca_pd *pd,
|
|
struct ib_ah_attr *ah_attr,
|
|
struct mthca_ah *ah);
|
|
int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
|
|
int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
|
|
struct ib_ud_header *header);
|
|
int mthca_ah_query(struct ib_ah *ibah, struct ib_ah_attr *attr);
|
|
int mthca_ah_grh_present(struct mthca_ah *ah);
|
|
u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
|
|
enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);
|
|
|
|
int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
|
|
int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
|
|
|
|
int mthca_process_mad(struct ib_device *ibdev,
|
|
int mad_flags,
|
|
u8 port_num,
|
|
struct ib_wc *in_wc,
|
|
struct ib_grh *in_grh,
|
|
struct ib_mad *in_mad,
|
|
struct ib_mad *out_mad);
|
|
int mthca_create_agents(struct mthca_dev *dev);
|
|
void mthca_free_agents(struct mthca_dev *dev);
|
|
|
|
static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
|
|
{
|
|
return container_of(ibdev, struct mthca_dev, ib_dev);
|
|
}
|
|
|
|
static inline int mthca_is_memfree(struct mthca_dev *dev)
|
|
{
|
|
return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
|
|
}
|
|
|
|
#endif /* MTHCA_DEV_H */
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