db5b716947
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
861 lines
22 KiB
C
861 lines
22 KiB
C
/*
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* linux/arch/arm/mm/mmu.c
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*
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* Copyright (C) 1995-2005 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mman.h>
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#include <linux/nodemask.h>
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#include <asm/mach-types.h>
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#include <asm/setup.h>
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#include <asm/sizes.h>
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#include <asm/tlb.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "mm.h"
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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extern void _stext, _etext, __data_start, _end;
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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/*
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* empty_zero_page is a special page that is used for
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* zero-initialized data and COW.
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*/
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struct page *empty_zero_page;
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EXPORT_SYMBOL(empty_zero_page);
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/*
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* The pmd table for the upper-most set of pages.
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*/
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pmd_t *top_pmd;
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#define CPOLICY_UNCACHED 0
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#define CPOLICY_BUFFERED 1
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#define CPOLICY_WRITETHROUGH 2
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#define CPOLICY_WRITEBACK 3
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#define CPOLICY_WRITEALLOC 4
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static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
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static unsigned int ecc_mask __initdata = 0;
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pgprot_t pgprot_user;
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pgprot_t pgprot_kernel;
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EXPORT_SYMBOL(pgprot_user);
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EXPORT_SYMBOL(pgprot_kernel);
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struct cachepolicy {
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const char policy[16];
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unsigned int cr_mask;
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unsigned int pmd;
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unsigned int pte;
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};
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static struct cachepolicy cache_policies[] __initdata = {
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{
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.policy = "uncached",
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.cr_mask = CR_W|CR_C,
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.pmd = PMD_SECT_UNCACHED,
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.pte = L_PTE_MT_UNCACHED,
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}, {
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.policy = "buffered",
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.cr_mask = CR_C,
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.pmd = PMD_SECT_BUFFERED,
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.pte = L_PTE_MT_BUFFERABLE,
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}, {
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.policy = "writethrough",
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.cr_mask = 0,
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.pmd = PMD_SECT_WT,
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.pte = L_PTE_MT_WRITETHROUGH,
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}, {
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.policy = "writeback",
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.cr_mask = 0,
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.pmd = PMD_SECT_WB,
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.pte = L_PTE_MT_WRITEBACK,
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}, {
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.policy = "writealloc",
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.cr_mask = 0,
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.pmd = PMD_SECT_WBWA,
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.pte = L_PTE_MT_WRITEALLOC,
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}
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};
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/*
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* These are useful for identifying cache coherency
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* problems by allowing the cache or the cache and
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* writebuffer to be turned off. (Note: the write
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* buffer should not be on and the cache off).
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*/
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static void __init early_cachepolicy(char **p)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
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int len = strlen(cache_policies[i].policy);
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if (memcmp(*p, cache_policies[i].policy, len) == 0) {
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cachepolicy = i;
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cr_alignment &= ~cache_policies[i].cr_mask;
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cr_no_alignment &= ~cache_policies[i].cr_mask;
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*p += len;
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break;
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}
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}
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if (i == ARRAY_SIZE(cache_policies))
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printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
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if (cpu_architecture() >= CPU_ARCH_ARMv6) {
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printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
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cachepolicy = CPOLICY_WRITEBACK;
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}
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flush_cache_all();
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set_cr(cr_alignment);
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}
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__early_param("cachepolicy=", early_cachepolicy);
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static void __init early_nocache(char **__unused)
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{
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char *p = "buffered";
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printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
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early_cachepolicy(&p);
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}
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__early_param("nocache", early_nocache);
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static void __init early_nowrite(char **__unused)
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{
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char *p = "uncached";
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printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
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early_cachepolicy(&p);
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}
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__early_param("nowb", early_nowrite);
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static void __init early_ecc(char **p)
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{
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if (memcmp(*p, "on", 2) == 0) {
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ecc_mask = PMD_PROTECTION;
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*p += 2;
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} else if (memcmp(*p, "off", 3) == 0) {
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ecc_mask = 0;
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*p += 3;
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}
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}
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__early_param("ecc=", early_ecc);
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static int __init noalign_setup(char *__unused)
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{
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cr_alignment &= ~CR_A;
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cr_no_alignment &= ~CR_A;
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set_cr(cr_alignment);
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return 1;
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}
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__setup("noalign", noalign_setup);
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#ifndef CONFIG_SMP
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void adjust_cr(unsigned long mask, unsigned long set)
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{
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unsigned long flags;
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mask &= ~CR_A;
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set &= mask;
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local_irq_save(flags);
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cr_no_alignment = (cr_no_alignment & ~mask) | set;
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cr_alignment = (cr_alignment & ~mask) | set;
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set_cr((get_cr() & ~mask) | set);
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local_irq_restore(flags);
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}
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#endif
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#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
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#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
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static struct mem_type mem_types[] = {
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[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
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L_PTE_SHARED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_CACHED] = { /* ioremap_cached */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_WC] = { /* ioremap_wc */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE,
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.domain = DOMAIN_IO,
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},
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[MT_CACHECLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
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.domain = DOMAIN_KERNEL,
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},
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[MT_MINICLEAN] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_LOW_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_EXEC,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_USER,
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},
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[MT_HIGH_VECTORS] = {
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.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
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L_PTE_USER | L_PTE_EXEC,
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.prot_l1 = PMD_TYPE_TABLE,
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.domain = DOMAIN_USER,
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},
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[MT_MEMORY] = {
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.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
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.domain = DOMAIN_KERNEL,
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},
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[MT_ROM] = {
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.prot_sect = PMD_TYPE_SECT,
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.domain = DOMAIN_KERNEL,
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},
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};
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const struct mem_type *get_mem_type(unsigned int type)
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{
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return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
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}
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/*
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* Adjust the PMD section entries according to the CPU in use.
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*/
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static void __init build_mem_type_table(void)
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{
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struct cachepolicy *cp;
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unsigned int cr = get_cr();
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unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
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int cpu_arch = cpu_architecture();
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int i;
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if (cpu_arch < CPU_ARCH_ARMv6) {
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#if defined(CONFIG_CPU_DCACHE_DISABLE)
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if (cachepolicy > CPOLICY_BUFFERED)
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cachepolicy = CPOLICY_BUFFERED;
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#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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if (cachepolicy > CPOLICY_WRITETHROUGH)
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cachepolicy = CPOLICY_WRITETHROUGH;
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#endif
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}
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if (cpu_arch < CPU_ARCH_ARMv5) {
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if (cachepolicy >= CPOLICY_WRITEALLOC)
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cachepolicy = CPOLICY_WRITEBACK;
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ecc_mask = 0;
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}
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#ifdef CONFIG_SMP
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cachepolicy = CPOLICY_WRITEALLOC;
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#endif
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/*
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* On non-Xscale3 ARMv5-and-older systems, use CB=01
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* (Uncached/Buffered) for ioremap_wc() mappings. On XScale3
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* and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable
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* in xsc3 parlance, Uncached Normal in ARMv6 parlance).
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*/
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if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
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mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
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mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
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}
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/*
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* ARMv5 and lower, bit 4 must be set for page tables.
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* (was: cache "update-able on write" bit on ARM610)
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* However, Xscale cores require this bit to be cleared.
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*/
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if (cpu_is_xscale()) {
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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mem_types[i].prot_sect &= ~PMD_BIT4;
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mem_types[i].prot_l1 &= ~PMD_BIT4;
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}
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} else if (cpu_arch < CPU_ARCH_ARMv6) {
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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if (mem_types[i].prot_l1)
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mem_types[i].prot_l1 |= PMD_BIT4;
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if (mem_types[i].prot_sect)
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mem_types[i].prot_sect |= PMD_BIT4;
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}
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}
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cp = &cache_policies[cachepolicy];
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vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
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#ifndef CONFIG_SMP
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/*
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* Only use write-through for non-SMP systems
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*/
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if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
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vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
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#endif
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/*
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* Enable CPU-specific coherency if supported.
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* (Only available on XSC3 at the moment.)
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*/
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if (arch_is_coherent()) {
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if (cpu_is_xsc3()) {
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
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}
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}
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/*
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* ARMv6 and above have extended page tables.
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*/
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if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
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/*
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* Mark cache clean areas and XIP ROM read only
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* from SVC mode and no access from userspace.
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*/
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mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
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/*
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* Mark the device area as "shared device"
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*/
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mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
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#ifdef CONFIG_SMP
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/*
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* Mark memory with the "shared" attribute for SMP systems
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*/
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user_pgprot |= L_PTE_SHARED;
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kern_pgprot |= L_PTE_SHARED;
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vecs_pgprot |= L_PTE_SHARED;
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mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
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#endif
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}
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for (i = 0; i < 16; i++) {
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unsigned long v = pgprot_val(protection_map[i]);
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protection_map[i] = __pgprot(v | user_pgprot);
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}
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mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
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mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
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if (cpu_arch < CPU_ARCH_ARMv5)
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mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
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pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
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pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
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L_PTE_DIRTY | L_PTE_WRITE |
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L_PTE_EXEC | kern_pgprot);
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mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
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mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
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mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
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mem_types[MT_ROM].prot_sect |= cp->pmd;
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switch (cp->pmd) {
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case PMD_SECT_WT:
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
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break;
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case PMD_SECT_WB:
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case PMD_SECT_WBWA:
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mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
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break;
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}
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printk("Memory policy: ECC %sabled, Data cache %s\n",
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ecc_mask ? "en" : "dis", cp->policy);
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for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
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struct mem_type *t = &mem_types[i];
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if (t->prot_l1)
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t->prot_l1 |= PMD_DOMAIN(t->domain);
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if (t->prot_sect)
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t->prot_sect |= PMD_DOMAIN(t->domain);
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}
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}
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#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
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static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
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unsigned long end, unsigned long pfn,
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const struct mem_type *type)
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{
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pte_t *pte;
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if (pmd_none(*pmd)) {
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pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
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__pmd_populate(pmd, __pa(pte) | type->prot_l1);
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}
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pte = pte_offset_kernel(pmd, addr);
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do {
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set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
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pfn++;
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} while (pte++, addr += PAGE_SIZE, addr != end);
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}
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static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
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unsigned long end, unsigned long phys,
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const struct mem_type *type)
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{
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pmd_t *pmd = pmd_offset(pgd, addr);
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/*
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* Try a section mapping - end, addr and phys must all be aligned
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* to a section boundary. Note that PMDs refer to the individual
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* L1 entries, whereas PGDs refer to a group of L1 entries making
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* up one logical pointer to an L2 table.
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*/
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if (((addr | end | phys) & ~SECTION_MASK) == 0) {
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pmd_t *p = pmd;
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if (addr & SECTION_SIZE)
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pmd++;
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do {
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*pmd = __pmd(phys | type->prot_sect);
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phys += SECTION_SIZE;
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} while (pmd++, addr += SECTION_SIZE, addr != end);
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flush_pmd_entry(p);
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} else {
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/*
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* No need to loop; pte's aren't interested in the
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* individual L1 entries.
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*/
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alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
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}
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}
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static void __init create_36bit_mapping(struct map_desc *md,
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const struct mem_type *type)
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{
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unsigned long phys, addr, length, end;
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pgd_t *pgd;
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addr = md->virtual;
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phys = (unsigned long)__pfn_to_phys(md->pfn);
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length = PAGE_ALIGN(md->length);
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if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
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printk(KERN_ERR "MM: CPU does not support supersection "
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"mapping for 0x%08llx at 0x%08lx\n",
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__pfn_to_phys((u64)md->pfn), addr);
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return;
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}
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/* N.B. ARMv6 supersections are only defined to work with domain 0.
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* Since domain assignments can in fact be arbitrary, the
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|
* 'domain == 0' check below is required to insure that ARMv6
|
|
* supersections are only allocated for domain 0 regardless
|
|
* of the actual domain assignments in use.
|
|
*/
|
|
if (type->domain) {
|
|
printk(KERN_ERR "MM: invalid domain in supersection "
|
|
"mapping for 0x%08llx at 0x%08lx\n",
|
|
__pfn_to_phys((u64)md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
|
|
printk(KERN_ERR "MM: cannot create mapping for "
|
|
"0x%08llx at 0x%08lx invalid alignment\n",
|
|
__pfn_to_phys((u64)md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Shift bits [35:32] of address into bits [23:20] of PMD
|
|
* (See ARMv6 spec).
|
|
*/
|
|
phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
end = addr + length;
|
|
do {
|
|
pmd_t *pmd = pmd_offset(pgd, addr);
|
|
int i;
|
|
|
|
for (i = 0; i < 16; i++)
|
|
*pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
|
|
|
|
addr += SUPERSECTION_SIZE;
|
|
phys += SUPERSECTION_SIZE;
|
|
pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
|
|
} while (addr != end);
|
|
}
|
|
|
|
/*
|
|
* Create the page directory entries and any necessary
|
|
* page tables for the mapping specified by `md'. We
|
|
* are able to cope here with varying sizes and address
|
|
* offsets, and we take full advantage of sections and
|
|
* supersections.
|
|
*/
|
|
void __init create_mapping(struct map_desc *md)
|
|
{
|
|
unsigned long phys, addr, length, end;
|
|
const struct mem_type *type;
|
|
pgd_t *pgd;
|
|
|
|
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
|
|
printk(KERN_WARNING "BUG: not creating mapping for "
|
|
"0x%08llx at 0x%08lx in user region\n",
|
|
__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
return;
|
|
}
|
|
|
|
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
|
|
md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
|
|
printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
|
|
"overlaps vmalloc space\n",
|
|
__pfn_to_phys((u64)md->pfn), md->virtual);
|
|
}
|
|
|
|
type = &mem_types[md->type];
|
|
|
|
/*
|
|
* Catch 36-bit addresses
|
|
*/
|
|
if (md->pfn >= 0x100000) {
|
|
create_36bit_mapping(md, type);
|
|
return;
|
|
}
|
|
|
|
addr = md->virtual & PAGE_MASK;
|
|
phys = (unsigned long)__pfn_to_phys(md->pfn);
|
|
length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
|
|
|
|
if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
|
|
printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
|
|
"be mapped using pages, ignoring.\n",
|
|
__pfn_to_phys(md->pfn), addr);
|
|
return;
|
|
}
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
end = addr + length;
|
|
do {
|
|
unsigned long next = pgd_addr_end(addr, end);
|
|
|
|
alloc_init_section(pgd, addr, next, phys, type);
|
|
|
|
phys += next - addr;
|
|
addr = next;
|
|
} while (pgd++, addr != end);
|
|
}
|
|
|
|
/*
|
|
* Create the architecture specific mappings
|
|
*/
|
|
void __init iotable_init(struct map_desc *io_desc, int nr)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < nr; i++)
|
|
create_mapping(io_desc + i);
|
|
}
|
|
|
|
static int __init check_membank_valid(struct membank *mb)
|
|
{
|
|
/*
|
|
* Check whether this memory region has non-zero size.
|
|
*/
|
|
if (mb->size == 0)
|
|
return 0;
|
|
|
|
/*
|
|
* Check whether this memory region would entirely overlap
|
|
* the vmalloc area.
|
|
*/
|
|
if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
|
|
printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
|
|
"(vmalloc region overlap).\n",
|
|
mb->start, mb->start + mb->size - 1);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Check whether this memory region would partially overlap
|
|
* the vmalloc area.
|
|
*/
|
|
if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
|
|
phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
|
|
unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
|
|
|
|
printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
|
|
"to -%.8lx (vmalloc region overlap).\n",
|
|
mb->start, mb->start + mb->size - 1,
|
|
mb->start + newsize - 1);
|
|
mb->size = newsize;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void __init sanity_check_meminfo(struct meminfo *mi)
|
|
{
|
|
int i;
|
|
int j;
|
|
|
|
for (i = 0, j = 0; i < mi->nr_banks; i++) {
|
|
if (check_membank_valid(&mi->bank[i]))
|
|
mi->bank[j++] = mi->bank[i];
|
|
}
|
|
mi->nr_banks = j;
|
|
}
|
|
|
|
static inline void prepare_page_table(struct meminfo *mi)
|
|
{
|
|
unsigned long addr;
|
|
|
|
/*
|
|
* Clear out all the mappings below the kernel image.
|
|
*/
|
|
for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
/* The XIP kernel is mapped in the module area -- skip over it */
|
|
addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
|
|
#endif
|
|
for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
/*
|
|
* Clear out all the kernel space mappings, except for the first
|
|
* memory bank, up to the end of the vmalloc region.
|
|
*/
|
|
for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
|
|
addr < VMALLOC_END; addr += PGDIR_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
}
|
|
|
|
/*
|
|
* Reserve the various regions of node 0
|
|
*/
|
|
void __init reserve_node_zero(pg_data_t *pgdat)
|
|
{
|
|
unsigned long res_size = 0;
|
|
|
|
/*
|
|
* Register the kernel text and data with bootmem.
|
|
* Note that this can only be in node 0.
|
|
*/
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start,
|
|
BOOTMEM_DEFAULT);
|
|
#else
|
|
reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext,
|
|
BOOTMEM_DEFAULT);
|
|
#endif
|
|
|
|
/*
|
|
* Reserve the page tables. These are already in use,
|
|
* and can only be in node 0.
|
|
*/
|
|
reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
|
|
PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
|
|
|
|
/*
|
|
* Hmm... This should go elsewhere, but we really really need to
|
|
* stop things allocating the low memory; ideally we need a better
|
|
* implementation of GFP_DMA which does not assume that DMA-able
|
|
* memory starts at zero.
|
|
*/
|
|
if (machine_is_integrator() || machine_is_cintegrator())
|
|
res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
|
|
|
|
/*
|
|
* These should likewise go elsewhere. They pre-reserve the
|
|
* screen memory region at the start of main system memory.
|
|
*/
|
|
if (machine_is_edb7211())
|
|
res_size = 0x00020000;
|
|
if (machine_is_p720t())
|
|
res_size = 0x00014000;
|
|
|
|
/* H1940 and RX3715 need to reserve this for suspend */
|
|
|
|
if (machine_is_h1940() || machine_is_rx3715()) {
|
|
reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
|
|
BOOTMEM_DEFAULT);
|
|
reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
|
|
BOOTMEM_DEFAULT);
|
|
}
|
|
|
|
#ifdef CONFIG_SA1111
|
|
/*
|
|
* Because of the SA1111 DMA bug, we want to preserve our
|
|
* precious DMA-able memory...
|
|
*/
|
|
res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
|
|
#endif
|
|
if (res_size)
|
|
reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
|
|
BOOTMEM_DEFAULT);
|
|
}
|
|
|
|
/*
|
|
* Set up device the mappings. Since we clear out the page tables for all
|
|
* mappings above VMALLOC_END, we will remove any debug device mappings.
|
|
* This means you have to be careful how you debug this function, or any
|
|
* called function. This means you can't use any function or debugging
|
|
* method which may touch any device, otherwise the kernel _will_ crash.
|
|
*/
|
|
static void __init devicemaps_init(struct machine_desc *mdesc)
|
|
{
|
|
struct map_desc map;
|
|
unsigned long addr;
|
|
void *vectors;
|
|
|
|
/*
|
|
* Allocate the vector page early.
|
|
*/
|
|
vectors = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
BUG_ON(!vectors);
|
|
|
|
for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
/*
|
|
* Map the kernel if it is XIP.
|
|
* It is always first in the modulearea.
|
|
*/
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
|
|
map.virtual = MODULE_START;
|
|
map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
|
|
map.type = MT_ROM;
|
|
create_mapping(&map);
|
|
#endif
|
|
|
|
/*
|
|
* Map the cache flushing regions.
|
|
*/
|
|
#ifdef FLUSH_BASE
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
|
|
map.virtual = FLUSH_BASE;
|
|
map.length = SZ_1M;
|
|
map.type = MT_CACHECLEAN;
|
|
create_mapping(&map);
|
|
#endif
|
|
#ifdef FLUSH_BASE_MINICACHE
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
|
|
map.virtual = FLUSH_BASE_MINICACHE;
|
|
map.length = SZ_1M;
|
|
map.type = MT_MINICLEAN;
|
|
create_mapping(&map);
|
|
#endif
|
|
|
|
/*
|
|
* Create a mapping for the machine vectors at the high-vectors
|
|
* location (0xffff0000). If we aren't using high-vectors, also
|
|
* create a mapping at the low-vectors virtual address.
|
|
*/
|
|
map.pfn = __phys_to_pfn(virt_to_phys(vectors));
|
|
map.virtual = 0xffff0000;
|
|
map.length = PAGE_SIZE;
|
|
map.type = MT_HIGH_VECTORS;
|
|
create_mapping(&map);
|
|
|
|
if (!vectors_high()) {
|
|
map.virtual = 0;
|
|
map.type = MT_LOW_VECTORS;
|
|
create_mapping(&map);
|
|
}
|
|
|
|
/*
|
|
* Ask the machine support to map in the statically mapped devices.
|
|
*/
|
|
if (mdesc->map_io)
|
|
mdesc->map_io();
|
|
|
|
/*
|
|
* Finally flush the caches and tlb to ensure that we're in a
|
|
* consistent state wrt the writebuffer. This also ensures that
|
|
* any write-allocated cache lines in the vector page are written
|
|
* back. After this point, we can start to touch devices again.
|
|
*/
|
|
local_flush_tlb_all();
|
|
flush_cache_all();
|
|
}
|
|
|
|
/*
|
|
* paging_init() sets up the page tables, initialises the zone memory
|
|
* maps, and sets up the zero page, bad page and bad page tables.
|
|
*/
|
|
void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
|
|
{
|
|
void *zero_page;
|
|
|
|
build_mem_type_table();
|
|
sanity_check_meminfo(mi);
|
|
prepare_page_table(mi);
|
|
bootmem_init(mi);
|
|
devicemaps_init(mdesc);
|
|
|
|
top_pmd = pmd_off_k(0xffff0000);
|
|
|
|
/*
|
|
* allocate the zero page. Note that we count on this going ok.
|
|
*/
|
|
zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
memzero(zero_page, PAGE_SIZE);
|
|
empty_zero_page = virt_to_page(zero_page);
|
|
flush_dcache_page(empty_zero_page);
|
|
}
|
|
|
|
/*
|
|
* In order to soft-boot, we need to insert a 1:1 mapping in place of
|
|
* the user-mode pages. This will then ensure that we have predictable
|
|
* results when turning the mmu off
|
|
*/
|
|
void setup_mm_for_reboot(char mode)
|
|
{
|
|
unsigned long base_pmdval;
|
|
pgd_t *pgd;
|
|
int i;
|
|
|
|
if (current->mm && current->mm->pgd)
|
|
pgd = current->mm->pgd;
|
|
else
|
|
pgd = init_mm.pgd;
|
|
|
|
base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
|
|
if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
|
|
base_pmdval |= PMD_BIT4;
|
|
|
|
for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
|
|
unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
|
|
pmd_t *pmd;
|
|
|
|
pmd = pmd_off(pgd, i << PGDIR_SHIFT);
|
|
pmd[0] = __pmd(pmdval);
|
|
pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
|
|
flush_pmd_entry(pmd);
|
|
}
|
|
}
|