4b3073e1c5
On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
302 lines
9.8 KiB
C
302 lines
9.8 KiB
C
/*
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* CRIS pgtable.h - macros and functions to manipulate page tables.
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*/
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#ifndef _CRIS_PGTABLE_H
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#define _CRIS_PGTABLE_H
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#include <asm/page.h>
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#include <asm-generic/pgtable-nopmd.h>
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <asm/mmu.h>
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#endif
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#include <arch/pgtable.h>
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* CRIS, we use that, but "fold" the mid level into the top-level page
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* table. Since the MMU TLB is software loaded through an interrupt, it
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* supports any page table structure, so we could have used a three-level
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* setup, but for the amounts of memory we normally use, a two-level is
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* probably more efficient.
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*
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* This file contains the functions and defines necessary to modify and use
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* the CRIS page table tree.
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*/
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#ifndef __ASSEMBLY__
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extern void paging_init(void);
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#endif
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/* Certain architectures need to do special things when pte's
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/*
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* (pmds are folded into pgds so this doesn't get actually called,
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* but the define is needed for a generic inline function.)
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*/
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
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/* PGDIR_SHIFT determines the size of the area a second-level page table can
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* map. It is equal to the page size times the number of PTE's that fit in
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* a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
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*/
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#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: we use a two-level, so
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* we don't really have any PMD directory physically.
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* pointers are 4 bytes so we can use the page size and
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* divide it by 4 (shift by 2).
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*/
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#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
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#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
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/* calculate how many PGD entries a user-level program can use
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* the first mappable virtual address is 0
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* (TASK_SIZE is the maximum virtual address space)
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*/
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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/* zero page used for uninitialized stuff */
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#ifndef __ASSEMBLY__
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extern unsigned long empty_zero_page;
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#endif
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/* number of bits that fit into a memory pointer */
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#define BITS_PER_PTR (8*sizeof(unsigned long))
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/* to align the pointer to a pointer address */
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#define PTR_MASK (~(sizeof(void*)-1))
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/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
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/* 64-bit machines, beware! SRB. */
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#define SIZEOF_PTR_LOG2 2
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/* to find an entry in a page-table */
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#define PAGE_PTR(address) \
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((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
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/* to set the page-dir */
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#define SET_PAGE_DIR(tsk,pgdir)
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
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#define pmd_none(x) (!pmd_val(x))
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/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
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* works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
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*/
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#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
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#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
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#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
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#ifndef __ASSEMBLY__
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
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static inline int pte_special(pte_t pte) { return 0; }
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
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return pte;
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
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return pte;
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
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return pte;
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= _PAGE_WRITE;
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if (pte_val(pte) & _PAGE_MODIFIED)
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pte_val(pte) |= _PAGE_SILENT_WRITE;
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return pte;
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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pte_val(pte) |= _PAGE_MODIFIED;
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if (pte_val(pte) & _PAGE_WRITE)
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pte_val(pte) |= _PAGE_SILENT_WRITE;
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return pte;
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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pte_val(pte) |= _PAGE_ACCESSED;
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if (pte_val(pte) & _PAGE_READ)
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{
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pte_val(pte) |= _PAGE_SILENT_READ;
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if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
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(_PAGE_WRITE | _PAGE_MODIFIED))
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pte_val(pte) |= _PAGE_SILENT_WRITE;
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}
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return pte;
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}
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static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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/* What actually goes as arguments to the various functions is less than
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* obvious, but a rule of thumb is that struct page's goes as struct page *,
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* really physical DRAM addresses are unsigned long's, and DRAM "virtual"
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* addresses (the 0xc0xxxxxx's) goes as void *'s.
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*/
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static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
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{
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pte_t pte;
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/* the PTE needs a physical address */
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pte_val(pte) = __pa(page) | pgprot_val(pgprot);
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return pte;
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}
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#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
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#define mk_pte_phys(physpage, pgprot) \
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({ \
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pte_t __pte; \
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\
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pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
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__pte; \
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})
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
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#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
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/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
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* __pte_page(pte_val) refers to the "virtual" DRAM interval
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* pte_pagenr refers to the page-number counted starting from the virtual DRAM start
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*/
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static inline unsigned long __pte_page(pte_t pte)
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{
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/* the PTE contains a physical address */
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return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
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}
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#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
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/* permanent address of a page */
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#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
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#define pte_page(pte) (mem_map+pte_pagenr(pte))
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/* only the pte's themselves need to point to physical DRAM (see above)
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* the pagetable links are purely handled within the kernel SW and thus
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* don't need the __pa and __va transformations.
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*/
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static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
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{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
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#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
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#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
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/* to find an entry in a page-table-directory. */
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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/* to find an entry in a page-table-directory */
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static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
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{
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return mm->pgd + pgd_index(address);
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}
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/* Find an entry in the third-level page table.. */
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#define __pte_offset(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
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#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
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#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
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/*
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* CRIS doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information.
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*
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* Actually I am not sure on what this could be used for.
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*/
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static inline void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t *ptep)
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{
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}
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/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
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/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
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#define __swp_type(x) (((x).val >> 5) & 0x7f)
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#define __swp_offset(x) ((x).val >> 12)
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#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define kern_addr_valid(addr) (1)
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#include <asm-generic/pgtable.h>
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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#define pte_to_pgoff(x) (pte_val(x) >> 6)
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#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE)
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typedef pte_t *pte_addr_t;
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#endif /* __ASSEMBLY__ */
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#endif /* _CRIS_PGTABLE_H */
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