3bebca2d20
now all BLKFIN should be BFIN, should be no functional changes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
435 lines
9.9 KiB
C
435 lines
9.9 KiB
C
/*
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* Blackfin CPLB initialization
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*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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u_long icplb_table[MAX_CPLBS+1];
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u_long dcplb_table[MAX_CPLBS+1];
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#ifdef CONFIG_CPLB_SWITCH_TAB_L1
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u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
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u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
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#ifdef CONFIG_CPLB_INFO
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u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
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u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
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#endif /* CONFIG_CPLB_INFO */
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#else
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u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
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u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
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#ifdef CONFIG_CPLB_INFO
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u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
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u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
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#endif /* CONFIG_CPLB_INFO */
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#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
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struct s_cplb {
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struct cplb_tab init_i;
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struct cplb_tab init_d;
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struct cplb_tab switch_i;
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struct cplb_tab switch_d;
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};
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#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
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static struct cplb_desc cplb_data[] = {
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{
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.start = 0,
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.end = SIZE_1K,
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.psize = SIZE_1K,
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.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
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.i_conf = SDRAM_OOPS,
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.d_conf = SDRAM_OOPS,
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#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
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.valid = 1,
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#else
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.valid = 0,
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#endif
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.name = "ZERO Pointer Saveguard",
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},
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{
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.start = L1_CODE_START,
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.end = L1_CODE_START + L1_CODE_LENGTH,
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.psize = SIZE_4M,
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.attr = INITIAL_T | SWITCH_T | I_CPLB,
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.i_conf = L1_IMEMORY,
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.d_conf = 0,
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.valid = 1,
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.name = "L1 I-Memory",
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},
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{
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.start = L1_DATA_A_START,
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.end = L1_DATA_B_START + L1_DATA_B_LENGTH,
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.psize = SIZE_4M,
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.attr = INITIAL_T | SWITCH_T | D_CPLB,
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.i_conf = 0,
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.d_conf = L1_DMEMORY,
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#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
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.valid = 1,
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#else
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.valid = 0,
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#endif
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.name = "L1 D-Memory",
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},
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{
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.start = 0,
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.end = 0, /* dynamic */
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.psize = 0,
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.attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
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.i_conf = SDRAM_IGENERIC,
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.d_conf = SDRAM_DGENERIC,
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.valid = 1,
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.name = "SDRAM Kernel",
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},
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{
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.start = 0, /* dynamic */
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.end = 0, /* dynamic */
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.psize = 0,
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.attr = INITIAL_T | SWITCH_T | D_CPLB,
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.i_conf = SDRAM_IGENERIC,
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.d_conf = SDRAM_DNON_CHBL,
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.valid = 1,
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.name = "SDRAM RAM MTD",
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},
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{
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.start = 0, /* dynamic */
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.end = 0, /* dynamic */
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.psize = SIZE_1M,
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.attr = INITIAL_T | SWITCH_T | D_CPLB,
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.d_conf = SDRAM_DNON_CHBL,
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.valid = 1,
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.name = "SDRAM Uncached DMA ZONE",
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},
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{
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.start = 0, /* dynamic */
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.end = 0, /* dynamic */
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.psize = 0,
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.attr = SWITCH_T | D_CPLB,
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.i_conf = 0, /* dynamic */
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.d_conf = 0, /* dynamic */
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.valid = 1,
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.name = "SDRAM Reserved Memory",
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},
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{
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.start = ASYNC_BANK0_BASE,
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.end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
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.psize = 0,
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.attr = SWITCH_T | D_CPLB,
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.d_conf = SDRAM_EBIU,
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.valid = 1,
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.name = "ASYNC Memory",
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},
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{
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#if defined(CONFIG_BF561)
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.start = L2_SRAM,
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.end = L2_SRAM_END,
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.psize = SIZE_1M,
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.attr = SWITCH_T | D_CPLB,
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.i_conf = L2_MEMORY,
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.d_conf = L2_MEMORY,
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.valid = 1,
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#else
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.valid = 0,
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#endif
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.name = "L2 Memory",
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}
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};
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static u16 __init lock_kernel_check(u32 start, u32 end)
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{
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if ((start <= (u32) _stext && end >= (u32) _end)
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|| (start >= (u32) _stext && end <= (u32) _end))
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return IN_KERNEL;
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return 0;
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}
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static unsigned short __init
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fill_cplbtab(struct cplb_tab *table,
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unsigned long start, unsigned long end,
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unsigned long block_size, unsigned long cplb_data)
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{
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int i;
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switch (block_size) {
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case SIZE_4M:
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i = 3;
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break;
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case SIZE_1M:
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i = 2;
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break;
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case SIZE_4K:
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i = 1;
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break;
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case SIZE_1K:
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default:
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i = 0;
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break;
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}
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cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
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while ((start < end) && (table->pos < table->size)) {
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table->tab[table->pos++] = start;
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if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
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table->tab[table->pos++] =
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cplb_data | CPLB_LOCK | CPLB_DIRTY;
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else
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table->tab[table->pos++] = cplb_data;
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start += block_size;
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}
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return 0;
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}
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static unsigned short __init
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close_cplbtab(struct cplb_tab *table)
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{
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while (table->pos < table->size) {
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table->tab[table->pos++] = 0;
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table->tab[table->pos++] = 0; /* !CPLB_VALID */
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}
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return 0;
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}
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/* helper function */
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static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
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{
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if (cplb_data[i].psize) {
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fill_cplbtab(t,
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cplb_data[i].start,
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cplb_data[i].end,
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cplb_data[i].psize,
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cplb_data[i].i_conf);
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} else {
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#if defined(CONFIG_BFIN_ICACHE)
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if (ANOMALY_05000263 && i == SDRAM_KERN) {
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fill_cplbtab(t,
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cplb_data[i].start,
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cplb_data[i].end,
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SIZE_4M,
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cplb_data[i].i_conf);
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} else
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#endif
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{
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fill_cplbtab(t,
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cplb_data[i].start,
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a_start,
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SIZE_1M,
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cplb_data[i].i_conf);
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fill_cplbtab(t,
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a_start,
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a_end,
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SIZE_4M,
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cplb_data[i].i_conf);
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fill_cplbtab(t, a_end,
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cplb_data[i].end,
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SIZE_1M,
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cplb_data[i].i_conf);
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}
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}
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}
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static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
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{
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if (cplb_data[i].psize) {
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fill_cplbtab(t,
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cplb_data[i].start,
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cplb_data[i].end,
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cplb_data[i].psize,
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cplb_data[i].d_conf);
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} else {
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fill_cplbtab(t,
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cplb_data[i].start,
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a_start, SIZE_1M,
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cplb_data[i].d_conf);
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fill_cplbtab(t, a_start,
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a_end, SIZE_4M,
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cplb_data[i].d_conf);
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fill_cplbtab(t, a_end,
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cplb_data[i].end,
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SIZE_1M,
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cplb_data[i].d_conf);
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}
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}
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void __init generate_cpl_tables(void)
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{
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u16 i, j, process;
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u32 a_start, a_end, as, ae, as_1m;
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struct cplb_tab *t_i = NULL;
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struct cplb_tab *t_d = NULL;
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struct s_cplb cplb;
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cplb.init_i.size = MAX_CPLBS;
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cplb.init_d.size = MAX_CPLBS;
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cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
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cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
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cplb.init_i.pos = 0;
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cplb.init_d.pos = 0;
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cplb.switch_i.pos = 0;
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cplb.switch_d.pos = 0;
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cplb.init_i.tab = icplb_table;
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cplb.init_d.tab = dcplb_table;
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cplb.switch_i.tab = ipdt_table;
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cplb.switch_d.tab = dpdt_table;
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cplb_data[SDRAM_KERN].end = memory_end;
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#ifdef CONFIG_MTD_UCLINUX
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cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
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cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
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cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
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# if defined(CONFIG_ROMFS_FS)
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cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
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/*
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* The ROMFS_FS size is often not multiple of 1MB.
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* This can cause multiple CPLB sets covering the same memory area.
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* This will then cause multiple CPLB hit exceptions.
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* Workaround: We ensure a contiguous memory area by extending the kernel
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* memory section over the mtd section.
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* For ROMFS_FS memory must be covered with ICPLBs anyways.
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* So there is no difference between kernel and mtd memory setup.
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*/
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cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
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cplb_data[SDRAM_RAM_MTD].valid = 0;
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# endif
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#else
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cplb_data[SDRAM_RAM_MTD].valid = 0;
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#endif
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cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
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cplb_data[SDRAM_DMAZ].end = _ramend;
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cplb_data[RES_MEM].start = _ramend;
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cplb_data[RES_MEM].end = physical_mem_end;
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if (reserved_mem_dcache_on)
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cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
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else
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cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
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if (reserved_mem_icache_on)
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cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
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else
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cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
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for (i = ZERO_P; i <= L2_MEM; i++) {
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if (!cplb_data[i].valid)
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continue;
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as_1m = cplb_data[i].start % SIZE_1M;
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/* We need to make sure all sections are properly 1M aligned
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* However between Kernel Memory and the Kernel mtd section, depending on the
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* rootfs size, there can be overlapping memory areas.
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*/
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if (as_1m && i != L1I_MEM && i != L1D_MEM) {
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#ifdef CONFIG_MTD_UCLINUX
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if (i == SDRAM_RAM_MTD) {
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if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
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cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
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else
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cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
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} else
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#endif
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printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
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cplb_data[i].name, cplb_data[i].start);
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}
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as = cplb_data[i].start % SIZE_4M;
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ae = cplb_data[i].end % SIZE_4M;
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if (as)
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a_start = cplb_data[i].start + (SIZE_4M - (as));
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else
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a_start = cplb_data[i].start;
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a_end = cplb_data[i].end - ae;
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for (j = INITIAL_T; j <= SWITCH_T; j++) {
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switch (j) {
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case INITIAL_T:
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if (cplb_data[i].attr & INITIAL_T) {
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t_i = &cplb.init_i;
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t_d = &cplb.init_d;
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process = 1;
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} else
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process = 0;
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break;
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case SWITCH_T:
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if (cplb_data[i].attr & SWITCH_T) {
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t_i = &cplb.switch_i;
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t_d = &cplb.switch_d;
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process = 1;
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} else
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process = 0;
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break;
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default:
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process = 0;
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break;
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}
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if (!process)
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continue;
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if (cplb_data[i].attr & I_CPLB)
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__fill_code_cplbtab(t_i, i, a_start, a_end);
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if (cplb_data[i].attr & D_CPLB)
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__fill_data_cplbtab(t_d, i, a_start, a_end);
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}
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}
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/* close tables */
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close_cplbtab(&cplb.init_i);
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close_cplbtab(&cplb.init_d);
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cplb.init_i.tab[cplb.init_i.pos] = -1;
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cplb.init_d.tab[cplb.init_d.pos] = -1;
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cplb.switch_i.tab[cplb.switch_i.pos] = -1;
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cplb.switch_d.tab[cplb.switch_d.pos] = -1;
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}
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#endif
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