4e950f6f01
Remove fs.h from mm.h. For this, 1) Uninline vma_wants_writenotify(). It's pretty huge anyway. 2) Add back fs.h or less bloated headers (err.h) to files that need it. As result, on x86_64 allyesconfig, fs.h dependencies cut down from 3929 files rebuilt down to 3444 (-12.3%). Cross-compile tested without regressions on my two usual configs and (sigh): alpha arm-mx1ads mips-bigsur powerpc-ebony alpha-allnoconfig arm-neponset mips-capcella powerpc-g5 alpha-defconfig arm-netwinder mips-cobalt powerpc-holly alpha-up arm-netx mips-db1000 powerpc-iseries arm arm-ns9xxx mips-db1100 powerpc-linkstation arm-assabet arm-omap_h2_1610 mips-db1200 powerpc-lite5200 arm-at91rm9200dk arm-onearm mips-db1500 powerpc-maple arm-at91rm9200ek arm-picotux200 mips-db1550 powerpc-mpc7448_hpc2 arm-at91sam9260ek arm-pleb mips-ddb5477 powerpc-mpc8272_ads arm-at91sam9261ek arm-pnx4008 mips-decstation powerpc-mpc8313_rdb arm-at91sam9263ek arm-pxa255-idp mips-e55 powerpc-mpc832x_mds arm-at91sam9rlek arm-realview mips-emma2rh powerpc-mpc832x_rdb arm-ateb9200 arm-realview-smp mips-excite powerpc-mpc834x_itx arm-badge4 arm-rpc mips-fulong powerpc-mpc834x_itxgp arm-carmeva arm-s3c2410 mips-ip22 powerpc-mpc834x_mds arm-cerfcube arm-shannon mips-ip27 powerpc-mpc836x_mds arm-clps7500 arm-shark mips-ip32 powerpc-mpc8540_ads arm-collie arm-simpad mips-jazz powerpc-mpc8544_ds arm-corgi arm-spitz mips-jmr3927 powerpc-mpc8560_ads arm-csb337 arm-trizeps4 mips-malta powerpc-mpc8568mds arm-csb637 arm-versatile mips-mipssim powerpc-mpc85xx_cds arm-ebsa110 i386 mips-mpc30x powerpc-mpc8641_hpcn arm-edb7211 i386-allnoconfig mips-msp71xx powerpc-mpc866_ads arm-em_x270 i386-defconfig mips-ocelot powerpc-mpc885_ads arm-ep93xx i386-up mips-pb1100 powerpc-pasemi arm-footbridge ia64 mips-pb1500 powerpc-pmac32 arm-fortunet ia64-allnoconfig mips-pb1550 powerpc-ppc64 arm-h3600 ia64-bigsur mips-pnx8550-jbs powerpc-prpmc2800 arm-h7201 ia64-defconfig mips-pnx8550-stb810 powerpc-ps3 arm-h7202 ia64-gensparse mips-qemu powerpc-pseries arm-hackkit ia64-sim mips-rbhma4200 powerpc-up arm-integrator ia64-sn2 mips-rbhma4500 s390 arm-iop13xx ia64-tiger mips-rm200 s390-allnoconfig arm-iop32x ia64-up mips-sb1250-swarm s390-defconfig arm-iop33x ia64-zx1 mips-sead s390-up arm-ixp2000 m68k mips-tb0219 sparc arm-ixp23xx m68k-amiga mips-tb0226 sparc-allnoconfig arm-ixp4xx m68k-apollo mips-tb0287 sparc-defconfig arm-jornada720 m68k-atari mips-workpad sparc-up arm-kafa m68k-bvme6000 mips-wrppmc sparc64 arm-kb9202 m68k-hp300 mips-yosemite sparc64-allnoconfig arm-ks8695 m68k-mac parisc sparc64-defconfig arm-lart m68k-mvme147 parisc-allnoconfig sparc64-up arm-lpd270 m68k-mvme16x parisc-defconfig um-x86_64 arm-lpd7a400 m68k-q40 parisc-up x86_64 arm-lpd7a404 m68k-sun3 powerpc x86_64-allnoconfig arm-lubbock m68k-sun3x powerpc-cell x86_64-defconfig arm-lusl7200 mips powerpc-celleb x86_64-up arm-mainstone mips-atlas powerpc-chrp32 Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
441 lines
11 KiB
C
441 lines
11 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2000, 2001 Kanoj Sarcar
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* Copyright (C) 2000, 2001 Ralf Baechle
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* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
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*/
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <asm/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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cpumask_t phys_cpu_present_map; /* Bitmask of available CPUs */
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volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
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cpumask_t cpu_online_map; /* Bitmask of currently online CPUs */
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int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
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int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
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EXPORT_SYMBOL(phys_cpu_present_map);
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EXPORT_SYMBOL(cpu_online_map);
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extern void __init calibrate_delay(void);
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extern void cpu_idle(void);
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/*
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* First C code run on the secondary CPUs after being started up by
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* the master.
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*/
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asmlinkage __cpuinit void start_secondary(void)
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{
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unsigned int cpu;
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Only do cpu_probe for first TC of CPU */
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if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
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#endif /* CONFIG_MIPS_MT_SMTC */
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cpu_probe();
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cpu_report();
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per_cpu_trap_init();
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prom_init_secondary();
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/*
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* XXX parity protection should be folded in here when it's converted
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* to an option instead of something based on .cputype
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*/
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calibrate_delay();
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preempt_disable();
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cpu = smp_processor_id();
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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prom_smp_finish();
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cpu_set(cpu, cpu_callin_map);
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cpu_idle();
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}
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DEFINE_SPINLOCK(smp_call_lock);
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struct call_data_struct *call_data;
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/*
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* Run a function on all other CPUs.
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* <func> The function to run. This must be fast and non-blocking.
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* <info> An arbitrary pointer to pass to the function.
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* <retry> If true, keep retrying until ready.
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* <wait> If true, wait until function has completed on other CPUs.
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* [RETURNS] 0 on success, else a negative status code.
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*
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* Does not return until remote CPUs are nearly ready to execute <func>
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* or are or have executed.
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*
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* You must not call this function with disabled interrupts or from a
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* hardware interrupt handler or from a bottom half handler:
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*
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* CPU A CPU B
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* Disable interrupts
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* smp_call_function()
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* Take call_lock
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* Send IPIs
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* Wait for all cpus to acknowledge IPI
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* CPU A has not responded, spin waiting
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* for cpu A to respond, holding call_lock
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* smp_call_function()
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* Spin waiting for call_lock
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* Deadlock Deadlock
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*/
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int smp_call_function (void (*func) (void *info), void *info, int retry,
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int wait)
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{
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struct call_data_struct data;
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int i, cpus = num_online_cpus() - 1;
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int cpu = smp_processor_id();
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/*
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* Can die spectacularly if this CPU isn't yet marked online
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*/
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BUG_ON(!cpu_online(cpu));
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if (!cpus)
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return 0;
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/* Can deadlock when called with interrupts disabled */
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WARN_ON(irqs_disabled());
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data.func = func;
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data.info = info;
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atomic_set(&data.started, 0);
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data.wait = wait;
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if (wait)
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atomic_set(&data.finished, 0);
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spin_lock(&smp_call_lock);
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call_data = &data;
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smp_mb();
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/* Send a message to all other CPUs and wait for them to respond */
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for_each_online_cpu(i)
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if (i != cpu)
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core_send_ipi(i, SMP_CALL_FUNCTION);
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/* Wait for response */
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/* FIXME: lock-up detection, backtrace on lock-up */
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while (atomic_read(&data.started) != cpus)
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barrier();
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if (wait)
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while (atomic_read(&data.finished) != cpus)
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barrier();
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call_data = NULL;
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spin_unlock(&smp_call_lock);
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return 0;
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}
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void smp_call_function_interrupt(void)
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{
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void (*func) (void *info) = call_data->func;
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void *info = call_data->info;
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int wait = call_data->wait;
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/*
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* Notify initiating CPU that I've grabbed the data and am
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* about to execute the function.
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*/
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smp_mb();
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atomic_inc(&call_data->started);
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/*
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* At this point the info structure may be out of scope unless wait==1.
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*/
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irq_enter();
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(*func)(info);
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irq_exit();
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if (wait) {
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smp_mb();
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atomic_inc(&call_data->finished);
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}
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}
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static void stop_this_cpu(void *dummy)
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{
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/*
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* Remove this CPU:
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*/
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cpu_clear(smp_processor_id(), cpu_online_map);
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local_irq_enable(); /* May need to service _machine_restart IPI */
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for (;;); /* Wait if available. */
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}
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void smp_send_stop(void)
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{
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smp_call_function(stop_this_cpu, NULL, 1, 0);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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prom_cpus_done();
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}
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/* called from main before smp_init() */
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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init_new_context(current, &init_mm);
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current_thread_info()->cpu = 0;
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plat_prepare_cpus(max_cpus);
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#ifndef CONFIG_HOTPLUG_CPU
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cpu_present_map = cpu_possible_map;
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#endif
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}
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/* preload SMP state for boot cpu */
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void __devinit smp_prepare_boot_cpu(void)
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{
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/*
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* This assumes that bootup is always handled by the processor
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* with the logic and physical number 0.
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*/
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__cpu_number_map[0] = 0;
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__cpu_logical_map[0] = 0;
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cpu_set(0, phys_cpu_present_map);
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cpu_set(0, cpu_online_map);
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cpu_set(0, cpu_callin_map);
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}
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/*
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* Called once for each "cpu_possible(cpu)". Needs to spin up the cpu
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* and keep control until "cpu_online(cpu)" is set. Note: cpu is
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* physical, not logical.
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*/
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int __cpuinit __cpu_up(unsigned int cpu)
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{
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struct task_struct *idle;
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/*
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* Processor goes to start_secondary(), sets online flag
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* The following code is purely to make sure
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* Linux can schedule processes on this slave.
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*/
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idle = fork_idle(cpu);
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if (IS_ERR(idle))
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panic(KERN_ERR "Fork failed for CPU %d", cpu);
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prom_boot_secondary(cpu, idle);
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/*
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* Trust is futile. We should really have timeouts ...
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*/
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while (!cpu_isset(cpu, cpu_callin_map))
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udelay(100);
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cpu_set(cpu, cpu_online_map);
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return 0;
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}
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/* Not really SMP stuff ... */
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int setup_profiling_timer(unsigned int multiplier)
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{
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return 0;
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}
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static void flush_tlb_all_ipi(void *info)
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{
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local_flush_tlb_all();
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(flush_tlb_all_ipi, NULL, 1, 1);
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}
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static void flush_tlb_mm_ipi(void *mm)
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{
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local_flush_tlb_mm((struct mm_struct *)mm);
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}
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/*
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* Special Variant of smp_call_function for use by TLB functions:
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*
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* o No return value
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* o collapses to normal function call on UP kernels
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* o collapses to normal function call on systems with a single shared
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* primary cache.
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* o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core.
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*/
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static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
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{
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#ifndef CONFIG_MIPS_MT_SMTC
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smp_call_function(func, info, 1, 1);
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#endif
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}
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static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
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{
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preempt_disable();
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smp_on_other_tlbs(func, info);
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func(info);
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preempt_enable();
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}
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/*
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* The following tlb flush calls are invoked when old translations are
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* being torn down, or pte attributes are changing. For single threaded
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* address spaces, a new context is obtained on the current cpu, and tlb
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* context on other cpus are invalidated to force a new context allocation
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* at switch_mm time, should the mm ever be used on other cpus. For
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* multithreaded address spaces, intercpu interrupts have to be sent.
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* Another case where intercpu interrupts are required is when the target
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* mm might be active on another cpu (eg debuggers doing the flushes on
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* behalf of debugees, kswapd stealing pages from another process etc).
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* Kanoj 07/00.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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smp_on_other_tlbs(flush_tlb_mm_ipi, (void *)mm);
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} else {
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int i;
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for (i = 0; i < num_online_cpus(); i++)
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if (smp_processor_id() != i)
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cpu_context(i, mm) = 0;
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}
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local_flush_tlb_mm(mm);
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preempt_enable();
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}
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struct flush_tlb_data {
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struct vm_area_struct *vma;
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unsigned long addr1;
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unsigned long addr2;
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};
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static void flush_tlb_range_ipi(void *info)
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{
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struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
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local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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struct flush_tlb_data fd;
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fd.vma = vma;
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fd.addr1 = start;
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fd.addr2 = end;
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smp_on_other_tlbs(flush_tlb_range_ipi, (void *)&fd);
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} else {
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int i;
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for (i = 0; i < num_online_cpus(); i++)
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if (smp_processor_id() != i)
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cpu_context(i, mm) = 0;
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}
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local_flush_tlb_range(vma, start, end);
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preempt_enable();
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}
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static void flush_tlb_kernel_range_ipi(void *info)
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{
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struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
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local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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struct flush_tlb_data fd;
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fd.addr1 = start;
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fd.addr2 = end;
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on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1);
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}
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static void flush_tlb_page_ipi(void *info)
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{
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struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
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local_flush_tlb_page(fd->vma, fd->addr1);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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preempt_disable();
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if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
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struct flush_tlb_data fd;
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fd.vma = vma;
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fd.addr1 = page;
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smp_on_other_tlbs(flush_tlb_page_ipi, (void *)&fd);
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} else {
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int i;
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for (i = 0; i < num_online_cpus(); i++)
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if (smp_processor_id() != i)
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cpu_context(i, vma->vm_mm) = 0;
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}
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local_flush_tlb_page(vma, page);
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preempt_enable();
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}
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static void flush_tlb_one_ipi(void *info)
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{
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unsigned long vaddr = (unsigned long) info;
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local_flush_tlb_one(vaddr);
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}
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void flush_tlb_one(unsigned long vaddr)
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{
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smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
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}
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EXPORT_SYMBOL(flush_tlb_page);
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EXPORT_SYMBOL(flush_tlb_one);
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