1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
782 lines
19 KiB
C
782 lines
19 KiB
C
/*
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*
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* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
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*
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* (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
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*
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*/
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#ifndef __MATROXFB_H__
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#define __MATROXFB_H__
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/* general, but fairly heavy, debugging */
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#undef MATROXFB_DEBUG
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/* heavy debugging: */
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/* -- logs putc[s], so everytime a char is displayed, it's logged */
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#undef MATROXFB_DEBUG_HEAVY
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/* This one _could_ cause infinite loops */
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/* It _does_ cause lots and lots of messages during idle loops */
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#undef MATROXFB_DEBUG_LOOP
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/* Debug register calls, too? */
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#undef MATROXFB_DEBUG_REG
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/* Guard accelerator accesses with spin_lock_irqsave... */
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#undef MATROXFB_USE_SPINLOCKS
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/console.h>
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#include <linux/selection.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/kd.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#ifdef CONFIG_MTRR
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#include <asm/mtrr.h>
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#endif
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#include "../console/fbcon.h"
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#if defined(CONFIG_PPC_PMAC)
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include "../macmodes.h"
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#endif
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/* always compile support for 32MB... It cost almost nothing */
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#define CONFIG_FB_MATROX_32MB
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#ifdef MATROXFB_DEBUG
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#define DEBUG
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#define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
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#ifdef MATROXFB_DEBUG_HEAVY
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#define DBG_HEAVY(x) DBG(x)
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#else /* MATROXFB_DEBUG_HEAVY */
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#define DBG_HEAVY(x) /* DBG_HEAVY */
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#endif /* MATROXFB_DEBUG_HEAVY */
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#ifdef MATROXFB_DEBUG_LOOP
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#define DBG_LOOP(x) DBG(x)
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#else /* MATROXFB_DEBUG_LOOP */
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#define DBG_LOOP(x) /* DBG_LOOP */
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#endif /* MATROXFB_DEBUG_LOOP */
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#ifdef MATROXFB_DEBUG_REG
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#define DBG_REG(x) DBG(x)
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#else /* MATROXFB_DEBUG_REG */
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#define DBG_REG(x) /* DBG_REG */
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#endif /* MATROXFB_DEBUG_REG */
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#else /* MATROXFB_DEBUG */
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#define DBG(x) /* DBG */
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#define DBG_HEAVY(x) /* DBG_HEAVY */
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#define DBG_REG(x) /* DBG_REG */
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#define DBG_LOOP(x) /* DBG_LOOP */
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#endif /* MATROXFB_DEBUG */
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#ifdef DEBUG
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#define dprintk(X...) printk(X)
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#else
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#define dprintk(X...)
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#endif
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#ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
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#define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
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#endif
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#ifndef PCI_SS_VENDOR_ID_MATROX
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#define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
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#endif
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#ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
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#define PCI_SS_ID_MATROX_GENERIC 0xFF00
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#define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
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#define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
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#define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
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#define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
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#define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
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#define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
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#define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
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#define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
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#define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
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#endif
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#define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
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#define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
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#define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
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#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
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/* G-series and Mystique have (almost) same DAC */
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#undef NEED_DAC1064
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#if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
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#define NEED_DAC1064 1
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#endif
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typedef struct {
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void __iomem* vaddr;
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} vaddr_t;
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static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
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return readb(va.vaddr + offs);
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}
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static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
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writeb(value, va.vaddr + offs);
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}
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static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
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writew(value, va.vaddr + offs);
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}
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static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
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return readl(va.vaddr + offs);
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}
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static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
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writel(value, va.vaddr + offs);
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}
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static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
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#if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
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/*
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* memcpy_toio works for us if:
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* (1) Copies data as 32bit quantities, not byte after byte,
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* (2) Performs LE ordered stores, and
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* (3) It copes with unaligned source (destination is guaranteed to be page
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* aligned and length is guaranteed to be multiple of 4).
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*/
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memcpy_toio(va.vaddr, src, len);
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#else
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u_int32_t __iomem* addr = va.vaddr;
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if ((unsigned long)src & 3) {
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while (len >= 4) {
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fb_writel(get_unaligned((u32 *)src), addr);
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addr++;
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len -= 4;
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src += 4;
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}
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} else {
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while (len >= 4) {
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fb_writel(*(u32 *)src, addr);
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addr++;
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len -= 4;
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src += 4;
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}
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}
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#endif
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}
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static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
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va->vaddr += offs;
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}
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static inline void __iomem* vaddr_va(vaddr_t va) {
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return va.vaddr;
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}
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#define MGA_IOREMAP_NORMAL 0
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#define MGA_IOREMAP_NOCACHE 1
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#define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
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#define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
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static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
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if (flags & MGA_IOREMAP_NOCACHE)
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virt->vaddr = ioremap_nocache(phys, size);
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else
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virt->vaddr = ioremap(phys, size);
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return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
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}
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static inline void mga_iounmap(vaddr_t va) {
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iounmap(va.vaddr);
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}
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struct my_timming {
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unsigned int pixclock;
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int mnp;
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unsigned int crtc;
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unsigned int HDisplay;
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unsigned int HSyncStart;
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unsigned int HSyncEnd;
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unsigned int HTotal;
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unsigned int VDisplay;
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unsigned int VSyncStart;
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unsigned int VSyncEnd;
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unsigned int VTotal;
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unsigned int sync;
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int dblscan;
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int interlaced;
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unsigned int delay; /* CRTC delay */
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};
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enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
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struct matrox_pll_cache {
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unsigned int valid;
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struct {
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unsigned int mnp_key;
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unsigned int mnp_value;
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} data[4];
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};
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struct matrox_pll_limits {
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unsigned int vcomin;
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unsigned int vcomax;
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};
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struct matrox_pll_features {
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unsigned int vco_freq_min;
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unsigned int ref_freq;
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unsigned int feed_div_min;
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unsigned int feed_div_max;
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unsigned int in_div_min;
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unsigned int in_div_max;
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unsigned int post_shift_max;
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};
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struct matroxfb_par
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{
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unsigned int final_bppShift;
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unsigned int cmap_len;
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struct {
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unsigned int bytes;
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unsigned int pixels;
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unsigned int chunks;
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} ydstorg;
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};
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struct matrox_fb_info;
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struct matrox_DAC1064_features {
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u_int8_t xvrefctrl;
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u_int8_t xmiscctrl;
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};
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struct matrox_accel_features {
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int has_cacheflush;
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};
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/* current hardware status */
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struct mavenregs {
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u_int8_t regs[256];
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int mode;
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int vlines;
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int xtal;
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int fv;
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u_int16_t htotal;
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u_int16_t hcorr;
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};
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struct matrox_crtc2 {
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u_int32_t ctl;
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};
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struct matrox_hw_state {
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u_int32_t MXoptionReg;
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unsigned char DACclk[6];
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unsigned char DACreg[80];
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unsigned char MiscOutReg;
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unsigned char DACpal[768];
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unsigned char CRTC[25];
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unsigned char CRTCEXT[9];
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unsigned char SEQ[5];
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/* unused for MGA mode, but who knows... */
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unsigned char GCTL[9];
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/* unused for MGA mode, but who knows... */
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unsigned char ATTR[21];
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/* TVOut only */
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struct mavenregs maven;
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struct matrox_crtc2 crtc2;
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};
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struct matrox_accel_data {
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#ifdef CONFIG_FB_MATROX_MILLENIUM
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unsigned char ramdac_rev;
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#endif
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u_int32_t m_dwg_rect;
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u_int32_t m_opmode;
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};
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struct v4l2_queryctrl;
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struct v4l2_control;
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struct matrox_altout {
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const char *name;
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int (*compute)(void* altout_dev, struct my_timming* input);
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int (*program)(void* altout_dev);
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int (*start)(void* altout_dev);
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int (*verifymode)(void* altout_dev, u_int32_t mode);
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int (*getqueryctrl)(void* altout_dev,
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struct v4l2_queryctrl* ctrl);
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int (*getctrl)(void* altout_dev,
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struct v4l2_control* ctrl);
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int (*setctrl)(void* altout_dev,
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struct v4l2_control* ctrl);
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};
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#define MATROXFB_SRC_NONE 0
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#define MATROXFB_SRC_CRTC1 1
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#define MATROXFB_SRC_CRTC2 2
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enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
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struct matrox_bios {
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unsigned int bios_valid : 1;
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unsigned int pins_len;
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unsigned char pins[128];
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struct {
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unsigned char vMaj, vMin, vRev;
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} version;
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struct {
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unsigned char state, tvout;
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} output;
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};
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extern struct display fb_display[];
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struct matrox_switch;
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struct matroxfb_driver;
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struct matroxfb_dh_fb_info;
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struct matrox_vsync {
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wait_queue_head_t wait;
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unsigned int cnt;
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};
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struct matrox_fb_info {
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struct fb_info fbcon;
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struct list_head next_fb;
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int dead;
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int initialized;
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unsigned int usecount;
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unsigned int userusecount;
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unsigned long irq_flags;
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struct matroxfb_par curr;
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struct matrox_hw_state hw;
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struct matrox_accel_data accel;
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struct pci_dev* pcidev;
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struct {
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struct matrox_vsync vsync;
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unsigned int pixclock;
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int mnp;
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int panpos;
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} crtc1;
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struct {
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struct matrox_vsync vsync;
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unsigned int pixclock;
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int mnp;
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struct matroxfb_dh_fb_info* info;
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struct rw_semaphore lock;
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} crtc2;
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struct {
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struct rw_semaphore lock;
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struct {
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int brightness, contrast, saturation, hue, gamma;
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int testout, deflicker;
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} tvo_params;
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} altout;
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#define MATROXFB_MAX_OUTPUTS 3
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struct {
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unsigned int src;
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struct matrox_altout* output;
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void* data;
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unsigned int mode;
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unsigned int default_src;
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} outputs[MATROXFB_MAX_OUTPUTS];
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#define MATROXFB_MAX_FB_DRIVERS 5
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struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
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void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
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unsigned int drivers_count;
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struct {
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unsigned long base; /* physical */
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vaddr_t vbase; /* CPU view */
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unsigned int len;
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unsigned int len_usable;
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unsigned int len_maximum;
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} video;
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struct {
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unsigned long base; /* physical */
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vaddr_t vbase; /* CPU view */
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unsigned int len;
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} mmio;
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unsigned int max_pixel_clock;
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struct matrox_switch* hw_switch;
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struct {
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struct matrox_pll_features pll;
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struct matrox_DAC1064_features DAC1064;
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struct matrox_accel_features accel;
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} features;
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struct {
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spinlock_t DAC;
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spinlock_t accel;
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} lock;
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enum mga_chip chip;
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int interleave;
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int millenium;
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int milleniumII;
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struct {
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int cfb4;
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const int* vxres;
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int cross4MB;
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int text;
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int plnwt;
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int srcorg;
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} capable;
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#ifdef CONFIG_MTRR
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struct {
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int vram;
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int vram_valid;
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} mtrr;
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#endif
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struct {
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int precise_width;
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int mga_24bpp_fix;
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int novga;
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int nobios;
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int nopciretry;
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int noinit;
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int sgram;
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#ifdef CONFIG_FB_MATROX_32MB
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int support32MB;
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#endif
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int accelerator;
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int text_type_aux;
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int video64bits;
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int crtc2;
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int maven_capable;
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unsigned int vgastep;
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unsigned int textmode;
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unsigned int textstep;
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unsigned int textvram; /* character cells */
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unsigned int ydstorg; /* offset in bytes from video start to usable memory */
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/* 0 except for 6MB Millenium */
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int memtype;
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int g450dac;
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int dfp_type;
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int panellink; /* G400 DFP possible (not G450/G550) */
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int dualhead;
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unsigned int fbResource;
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} devflags;
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struct fb_ops fbops;
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struct matrox_bios bios;
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struct {
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struct matrox_pll_limits pixel;
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struct matrox_pll_limits system;
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struct matrox_pll_limits video;
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} limits;
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struct {
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struct matrox_pll_cache pixel;
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struct matrox_pll_cache system;
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struct matrox_pll_cache video;
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} cache;
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struct {
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struct {
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unsigned int video;
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unsigned int system;
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} pll;
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struct {
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u_int32_t opt;
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u_int32_t opt2;
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u_int32_t opt3;
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u_int32_t mctlwtst;
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u_int32_t mctlwtst_core;
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u_int32_t memmisc;
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u_int32_t memrdbk;
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u_int32_t maccess;
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} reg;
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struct {
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unsigned int ddr:1,
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emrswen:1,
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dll:1;
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} memory;
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|
} values;
|
|
u_int32_t cmap[17];
|
|
};
|
|
|
|
#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
|
|
|
|
#ifdef CONFIG_FB_MATROX_MULTIHEAD
|
|
#define ACCESS_FBINFO2(info, x) (info->x)
|
|
#define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
|
|
|
|
#define MINFO minfo
|
|
|
|
#define WPMINFO2 struct matrox_fb_info* minfo
|
|
#define WPMINFO WPMINFO2 ,
|
|
#define CPMINFO2 const struct matrox_fb_info* minfo
|
|
#define CPMINFO CPMINFO2 ,
|
|
#define PMINFO2 minfo
|
|
#define PMINFO PMINFO2 ,
|
|
|
|
#define MINFO_FROM(x) struct matrox_fb_info* minfo = x
|
|
#else
|
|
|
|
extern struct matrox_fb_info matroxfb_global_mxinfo;
|
|
|
|
#define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
|
|
#define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
|
|
|
|
#define MINFO (&matroxfb_global_mxinfo)
|
|
|
|
#define WPMINFO2 void
|
|
#define WPMINFO
|
|
#define CPMINFO2 void
|
|
#define CPMINFO
|
|
#define PMINFO2
|
|
#define PMINFO
|
|
|
|
#define MINFO_FROM(x)
|
|
|
|
#endif
|
|
|
|
#define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
|
|
|
|
struct matrox_switch {
|
|
int (*preinit)(WPMINFO2);
|
|
void (*reset)(WPMINFO2);
|
|
int (*init)(WPMINFO struct my_timming*);
|
|
void (*restore)(WPMINFO2);
|
|
};
|
|
|
|
struct matroxfb_driver {
|
|
struct list_head node;
|
|
char* name;
|
|
void* (*probe)(struct matrox_fb_info* info);
|
|
void (*remove)(struct matrox_fb_info* info, void* data);
|
|
};
|
|
|
|
int matroxfb_register_driver(struct matroxfb_driver* drv);
|
|
void matroxfb_unregister_driver(struct matroxfb_driver* drv);
|
|
|
|
#define PCI_OPTION_REG 0x40
|
|
#define PCI_OPTION_ENABLE_ROM 0x40000000
|
|
|
|
#define PCI_MGA_INDEX 0x44
|
|
#define PCI_MGA_DATA 0x48
|
|
#define PCI_OPTION2_REG 0x50
|
|
#define PCI_OPTION3_REG 0x54
|
|
#define PCI_MEMMISC_REG 0x58
|
|
|
|
#define M_DWGCTL 0x1C00
|
|
#define M_MACCESS 0x1C04
|
|
#define M_CTLWTST 0x1C08
|
|
|
|
#define M_PLNWT 0x1C1C
|
|
|
|
#define M_BCOL 0x1C20
|
|
#define M_FCOL 0x1C24
|
|
|
|
#define M_SGN 0x1C58
|
|
#define M_LEN 0x1C5C
|
|
#define M_AR0 0x1C60
|
|
#define M_AR1 0x1C64
|
|
#define M_AR2 0x1C68
|
|
#define M_AR3 0x1C6C
|
|
#define M_AR4 0x1C70
|
|
#define M_AR5 0x1C74
|
|
#define M_AR6 0x1C78
|
|
|
|
#define M_CXBNDRY 0x1C80
|
|
#define M_FXBNDRY 0x1C84
|
|
#define M_YDSTLEN 0x1C88
|
|
#define M_PITCH 0x1C8C
|
|
#define M_YDST 0x1C90
|
|
#define M_YDSTORG 0x1C94
|
|
#define M_YTOP 0x1C98
|
|
#define M_YBOT 0x1C9C
|
|
|
|
/* mystique only */
|
|
#define M_CACHEFLUSH 0x1FFF
|
|
|
|
#define M_EXEC 0x0100
|
|
|
|
#define M_DWG_TRAP 0x04
|
|
#define M_DWG_BITBLT 0x08
|
|
#define M_DWG_ILOAD 0x09
|
|
|
|
#define M_DWG_LINEAR 0x0080
|
|
#define M_DWG_SOLID 0x0800
|
|
#define M_DWG_ARZERO 0x1000
|
|
#define M_DWG_SGNZERO 0x2000
|
|
#define M_DWG_SHIFTZERO 0x4000
|
|
|
|
#define M_DWG_REPLACE 0x000C0000
|
|
#define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
|
|
#define M_DWG_XOR 0x00060010
|
|
|
|
#define M_DWG_BFCOL 0x04000000
|
|
#define M_DWG_BMONOWF 0x08000000
|
|
|
|
#define M_DWG_TRANSC 0x40000000
|
|
|
|
#define M_FIFOSTATUS 0x1E10
|
|
#define M_STATUS 0x1E14
|
|
#define M_ICLEAR 0x1E18
|
|
#define M_IEN 0x1E1C
|
|
|
|
#define M_VCOUNT 0x1E20
|
|
|
|
#define M_RESET 0x1E40
|
|
#define M_MEMRDBK 0x1E44
|
|
|
|
#define M_AGP2PLL 0x1E4C
|
|
|
|
#define M_OPMODE 0x1E54
|
|
#define M_OPMODE_DMA_GEN_WRITE 0x00
|
|
#define M_OPMODE_DMA_BLIT 0x04
|
|
#define M_OPMODE_DMA_VECTOR_WRITE 0x08
|
|
#define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
|
|
#define M_OPMODE_DMA_BE_8BPP 0x0000
|
|
#define M_OPMODE_DMA_BE_16BPP 0x0100
|
|
#define M_OPMODE_DMA_BE_32BPP 0x0200
|
|
#define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
|
|
#define M_OPMODE_DIR_BE_8BPP 0x000000
|
|
#define M_OPMODE_DIR_BE_16BPP 0x010000
|
|
#define M_OPMODE_DIR_BE_32BPP 0x020000
|
|
|
|
#define M_ATTR_INDEX 0x1FC0
|
|
#define M_ATTR_DATA 0x1FC1
|
|
|
|
#define M_MISC_REG 0x1FC2
|
|
#define M_3C2_RD 0x1FC2
|
|
|
|
#define M_SEQ_INDEX 0x1FC4
|
|
#define M_SEQ_DATA 0x1FC5
|
|
|
|
#define M_MISC_REG_READ 0x1FCC
|
|
|
|
#define M_GRAPHICS_INDEX 0x1FCE
|
|
#define M_GRAPHICS_DATA 0x1FCF
|
|
|
|
#define M_CRTC_INDEX 0x1FD4
|
|
|
|
#define M_ATTR_RESET 0x1FDA
|
|
#define M_3DA_WR 0x1FDA
|
|
#define M_INSTS1 0x1FDA
|
|
|
|
#define M_EXTVGA_INDEX 0x1FDE
|
|
#define M_EXTVGA_DATA 0x1FDF
|
|
|
|
/* G200 only */
|
|
#define M_SRCORG 0x2CB4
|
|
#define M_DSTORG 0x2CB8
|
|
|
|
#define M_RAMDAC_BASE 0x3C00
|
|
|
|
/* fortunately, same on TVP3026 and MGA1064 */
|
|
#define M_DAC_REG (M_RAMDAC_BASE+0)
|
|
#define M_DAC_VAL (M_RAMDAC_BASE+1)
|
|
#define M_PALETTE_MASK (M_RAMDAC_BASE+2)
|
|
|
|
#define M_X_INDEX 0x00
|
|
#define M_X_DATAREG 0x0A
|
|
|
|
#define DAC_XGENIOCTRL 0x2A
|
|
#define DAC_XGENIODATA 0x2B
|
|
|
|
#define M_C2CTL 0x3C10
|
|
|
|
#define MX_OPTION_BSWAP 0x00000000
|
|
|
|
#ifdef __LITTLE_ENDIAN
|
|
#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
|
|
#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
|
|
#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
|
|
#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
|
|
#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
|
|
#else
|
|
#ifdef __BIG_ENDIAN
|
|
#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
|
|
#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
|
|
#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
|
|
#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
|
|
#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
|
|
#else
|
|
#error "Byte ordering have to be defined. Cannot continue."
|
|
#endif
|
|
#endif
|
|
|
|
#define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
|
|
#define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
|
|
#define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
|
|
#define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
|
|
#define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
|
|
#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
|
|
#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
|
|
|
|
#define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
|
|
|
|
#define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
|
|
|
|
/* code speedup */
|
|
#ifdef CONFIG_FB_MATROX_MILLENIUM
|
|
#define isInterleave(x) (x->interleave)
|
|
#define isMillenium(x) (x->millenium)
|
|
#define isMilleniumII(x) (x->milleniumII)
|
|
#else
|
|
#define isInterleave(x) (0)
|
|
#define isMillenium(x) (0)
|
|
#define isMilleniumII(x) (0)
|
|
#endif
|
|
|
|
#define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
|
|
#define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
|
|
#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
|
|
#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
|
|
extern void matroxfb_DAC_out(CPMINFO int reg, int val);
|
|
extern int matroxfb_DAC_in(CPMINFO int reg);
|
|
extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
|
|
extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
|
|
extern int matroxfb_enable_irq(WPMINFO int reenable);
|
|
|
|
#ifdef MATROXFB_USE_SPINLOCKS
|
|
#define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
|
|
#define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
|
|
#define CRITFLAGS unsigned long critflags;
|
|
#else
|
|
#define CRITBEGIN
|
|
#define CRITEND
|
|
#define CRITFLAGS
|
|
#endif
|
|
|
|
#endif /* __MATROXFB_H__ */
|