9d4c826259
This patch removes the sh778x specific pci code that pokes in the interrupt controller and overwrites things. The new and improved IRL code manages this in plat_irq_setup() and plat_irq_setup_pins() instead. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
162 lines
4.7 KiB
C
162 lines
4.7 KiB
C
/*
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* Low-Level PCI Support for the SH7780
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*
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* Dustin McIntire (dustin@sensoria.com)
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* Derived from arch/i386/kernel/pci-*.c which bore the message:
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*
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* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
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* With cleanup by Paul van Gool <pvangool@mimotech.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#undef DEBUG
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include "pci-sh4.h"
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#define INTC_BASE 0xffd00000
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#define INTC_ICR0 (INTC_BASE+0x0)
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#define INTC_ICR1 (INTC_BASE+0x1c)
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#define INTC_INTPRI (INTC_BASE+0x10)
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#define INTC_INTREQ (INTC_BASE+0x24)
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#define INTC_INTMSK0 (INTC_BASE+0x44)
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#define INTC_INTMSK1 (INTC_BASE+0x48)
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#define INTC_INTMSK2 (INTC_BASE+0x40080)
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#define INTC_INTMSKCLR0 (INTC_BASE+0x64)
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#define INTC_INTMSKCLR1 (INTC_BASE+0x68)
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#define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
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#define INTC_INT2MSKR (INTC_BASE+0x40038)
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#define INTC_INT2MSKCR (INTC_BASE+0x4003c)
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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* to access config space.
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*
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* Note that the platform specific initialization (BSC registers, and memory
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* space mapping) will be called via the platform defined function
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* pcibios_init_platform().
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*/
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static int __init sh7780_pci_init(void)
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{
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unsigned int id;
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int ret, match = 0;
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pr_debug("PCI: Starting intialization.\n");
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outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
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/* check for SH7780/SH7780R hardware */
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id = pci_read_reg(SH7780_PCIVID);
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if ((id & 0xffff) == SH7780_VENDOR_ID) {
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switch ((id >> 16) & 0xffff) {
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case SH7780_DEVICE_ID:
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case SH7781_DEVICE_ID:
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case SH7785_DEVICE_ID:
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match = 1;
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break;
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}
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}
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if (unlikely(!match)) {
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printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
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return -ENODEV;
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}
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/* Setup the INTC */
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if (mach_is_7780se()) {
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/* ICR0: IRL=use separately */
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ctrl_outl(0x00C00020, INTC_ICR0);
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/* ICR1: detect low level(for 2ndcut) */
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ctrl_outl(0xAAAA0000, INTC_ICR1);
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/* INTPRI: priority=3(all) */
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ctrl_outl(0x33333333, INTC_INTPRI);
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}
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if ((ret = sh4_pci_check_direct()) != 0)
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return ret;
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return pcibios_init_platform();
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}
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core_initcall(sh7780_pci_init);
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int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
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{
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u32 word;
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/*
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* This code is unused for some boards as it is done in the
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* bootloader and doing it here means the MAC addresses loaded
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* by the bootloader get lost.
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*/
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if (!(map->flags & SH4_PCIC_NO_RESET)) {
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/* toggle PCI reset pin */
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word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
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pci_write_reg(word, SH4_PCICR);
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/* Wait for a long time... not 1 sec. but long enough */
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mdelay(100);
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word = SH4_PCICR_PREFIX;
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pci_write_reg(word, SH4_PCICR);
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}
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/* set the command/status bits to:
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* Wait Cycle Control + Parity Enable + Bus Master +
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* Mem space enable
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*/
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pci_write_reg(0x00000046, SH7780_PCICMD);
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/* define this host as the host bridge */
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word = PCI_BASE_CLASS_BRIDGE << 24;
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pci_write_reg(word, SH7780_PCIRID);
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/* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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* Window0 = map->window0.size @ non-cached area base = SDRAM
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* Window1 = map->window1.size @ cached area base = SDRAM
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*/
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word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
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pci_write_reg(0x07f00001, SH4_PCILSR0);
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word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
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pci_write_reg(0x00000001, SH4_PCILSR1);
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/* Set the values on window 0 PCI config registers */
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word = P2SEGADDR(map->window0.base);
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pci_write_reg(0xa8000000, SH4_PCILAR0);
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pci_write_reg(0x08000000, SH7780_PCIMBAR0);
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/* Set the values on window 1 PCI config registers */
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word = P2SEGADDR(map->window1.base);
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pci_write_reg(0x00000000, SH4_PCILAR1);
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pci_write_reg(0x00000000, SH7780_PCIMBAR1);
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/* Map IO space into PCI IO window
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* The IO window is 64K-PCIBIOS_MIN_IO in size
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* IO addresses will be translated to the
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* PCI IO window base address
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*/
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pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
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PCIBIOS_MIN_IO, (64 << 10),
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SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
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/* NOTE: I'm ignoring the PCI error IRQs for now..
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* TODO: add support for the internal error interrupts and
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* DMA interrupts...
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*/
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/* Apply any last-minute PCIC fixups */
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pci_fixup_pcic();
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/* SH7780 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
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pci_write_reg(word, SH4_PCICR);
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return 1;
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}
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