7a9978a1e2
The IDE platform device is registered in three different places (2 board files for DM644x and in dm646x.c for DM646x) while both the IDE base address and the IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE platform seems to be in devices.c. Merge the IDE platform data and registration code and create davinci_init_ide() in place of dm646x_init_ide()... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
778 lines
17 KiB
C
778 lines
17 KiB
C
/*
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* TI DaVinci DM646X EVM board
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*
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* Derived from: arch/arm/mach-davinci/board-evm.c
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* Copyright (C) 2006 Texas Instruments.
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*
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* (C) 2007-2008, MontaVista Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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/**************************************************************************
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* Included Files
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**************************************************************************/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/leds.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c/at24.h>
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#include <linux/i2c/pcf857x.h>
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#include <media/tvp514x.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/clk.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/dm646x.h>
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#include <mach/common.h>
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#include <mach/serial.h>
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#include <mach/i2c.h>
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#include <mach/nand.h>
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#include <mach/clock.h>
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#include <mach/cdce949.h>
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#include "clock.h"
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#define NAND_BLOCK_SIZE SZ_128K
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/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
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* and U-Boot environment this avoids dependency on any particular combination
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* of UBL, U-Boot or flashing tools etc.
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*/
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static struct mtd_partition davinci_nand_partitions[] = {
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{
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/* UBL, U-Boot with environment */
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.name = "bootloader",
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.offset = MTDPART_OFS_APPEND,
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.size = 16 * NAND_BLOCK_SIZE,
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.mask_flags = MTD_WRITEABLE, /* force read-only */
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}, {
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_4M,
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.mask_flags = 0,
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}, {
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.name = "filesystem",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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.mask_flags = 0,
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}
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};
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static struct davinci_nand_pdata davinci_nand_data = {
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.mask_cle = 0x80000,
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.mask_ale = 0x40000,
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.parts = davinci_nand_partitions,
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.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
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.ecc_mode = NAND_ECC_HW,
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.options = 0,
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};
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static struct resource davinci_nand_resources[] = {
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{
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.start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
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.end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = DM646X_ASYNC_EMIF_CONTROL_BASE,
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.end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device davinci_nand_device = {
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.name = "davinci_nand",
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.id = 0,
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.num_resources = ARRAY_SIZE(davinci_nand_resources),
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.resource = davinci_nand_resources,
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.dev = {
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.platform_data = &davinci_nand_data,
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},
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};
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#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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#define HAS_ATA 1
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#else
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#define HAS_ATA 0
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#endif
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/* CPLD Register 0 bits to control ATA */
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#define DM646X_EVM_ATA_RST BIT(0)
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#define DM646X_EVM_ATA_PWD BIT(1)
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/* CPLD Register 0 Client: used for I/O Control */
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static int cpld_reg0_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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if (HAS_ATA) {
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u8 data;
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struct i2c_msg msg[2] = {
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{
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.addr = client->addr,
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.flags = I2C_M_RD,
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.len = 1,
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.buf = &data,
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},
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{
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.addr = client->addr,
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.flags = 0,
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.len = 1,
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.buf = &data,
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},
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};
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/* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
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i2c_transfer(client->adapter, msg, 1);
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data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
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i2c_transfer(client->adapter, msg + 1, 1);
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}
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return 0;
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}
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static const struct i2c_device_id cpld_reg_ids[] = {
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{ "cpld_reg0", 0, },
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{ },
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};
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static struct i2c_driver dm6467evm_cpld_driver = {
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.driver.name = "cpld_reg0",
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.id_table = cpld_reg_ids,
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.probe = cpld_reg0_probe,
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};
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/* LEDS */
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static struct gpio_led evm_leds[] = {
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{ .name = "DS1", .active_low = 1, },
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{ .name = "DS2", .active_low = 1, },
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{ .name = "DS3", .active_low = 1, },
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{ .name = "DS4", .active_low = 1, },
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};
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static const struct gpio_led_platform_data evm_led_data = {
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.num_leds = ARRAY_SIZE(evm_leds),
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.leds = evm_leds,
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};
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static struct platform_device *evm_led_dev;
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static int evm_led_setup(struct i2c_client *client, int gpio,
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unsigned int ngpio, void *c)
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{
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struct gpio_led *leds = evm_leds;
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int status;
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while (ngpio--) {
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leds->gpio = gpio++;
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leds++;
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};
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evm_led_dev = platform_device_alloc("leds-gpio", 0);
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platform_device_add_data(evm_led_dev, &evm_led_data,
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sizeof(evm_led_data));
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evm_led_dev->dev.parent = &client->dev;
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status = platform_device_add(evm_led_dev);
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if (status < 0) {
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platform_device_put(evm_led_dev);
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evm_led_dev = NULL;
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}
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return status;
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}
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static int evm_led_teardown(struct i2c_client *client, int gpio,
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unsigned ngpio, void *c)
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{
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if (evm_led_dev) {
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platform_device_unregister(evm_led_dev);
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evm_led_dev = NULL;
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}
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return 0;
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}
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static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
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static int evm_sw_setup(struct i2c_client *client, int gpio,
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unsigned ngpio, void *c)
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{
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int status;
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int i;
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char label[10];
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for (i = 0; i < 4; ++i) {
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snprintf(label, 10, "user_sw%d", i);
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status = gpio_request(gpio, label);
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if (status)
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goto out_free;
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evm_sw_gpio[i] = gpio++;
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status = gpio_direction_input(evm_sw_gpio[i]);
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if (status) {
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gpio_free(evm_sw_gpio[i]);
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evm_sw_gpio[i] = -EINVAL;
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goto out_free;
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}
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status = gpio_export(evm_sw_gpio[i], 0);
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if (status) {
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gpio_free(evm_sw_gpio[i]);
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evm_sw_gpio[i] = -EINVAL;
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goto out_free;
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}
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}
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return status;
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out_free:
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for (i = 0; i < 4; ++i) {
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if (evm_sw_gpio[i] != -EINVAL) {
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gpio_free(evm_sw_gpio[i]);
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evm_sw_gpio[i] = -EINVAL;
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}
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}
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return status;
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}
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static int evm_sw_teardown(struct i2c_client *client, int gpio,
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unsigned ngpio, void *c)
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{
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int i;
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for (i = 0; i < 4; ++i) {
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if (evm_sw_gpio[i] != -EINVAL) {
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gpio_unexport(evm_sw_gpio[i]);
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gpio_free(evm_sw_gpio[i]);
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evm_sw_gpio[i] = -EINVAL;
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}
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}
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return 0;
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}
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static int evm_pcf_setup(struct i2c_client *client, int gpio,
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unsigned int ngpio, void *c)
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{
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int status;
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if (ngpio < 8)
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return -EINVAL;
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status = evm_sw_setup(client, gpio, 4, c);
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if (status)
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return status;
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return evm_led_setup(client, gpio+4, 4, c);
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}
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static int evm_pcf_teardown(struct i2c_client *client, int gpio,
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unsigned int ngpio, void *c)
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{
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BUG_ON(ngpio < 8);
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evm_sw_teardown(client, gpio, 4, c);
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evm_led_teardown(client, gpio+4, 4, c);
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return 0;
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}
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static struct pcf857x_platform_data pcf_data = {
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.gpio_base = DAVINCI_N_GPIO+1,
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.setup = evm_pcf_setup,
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.teardown = evm_pcf_teardown,
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};
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/* Most of this EEPROM is unused, but U-Boot uses some data:
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* - 0x7f00, 6 bytes Ethernet Address
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* - ... newer boards may have more
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*/
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static struct at24_platform_data eeprom_info = {
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.byte_len = (256*1024) / 8,
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.page_size = 64,
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.flags = AT24_FLAG_ADDR16,
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.setup = davinci_get_mac_addr,
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.context = (void *)0x7f00,
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};
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static u8 dm646x_iis_serializer_direction[] = {
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TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
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};
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static u8 dm646x_dit_serializer_direction[] = {
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TX_MODE,
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};
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static struct snd_platform_data dm646x_evm_snd_data[] = {
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{
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.tx_dma_offset = 0x400,
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.rx_dma_offset = 0x400,
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.op_mode = DAVINCI_MCASP_IIS_MODE,
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.num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
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.tdm_slots = 2,
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.serial_dir = dm646x_iis_serializer_direction,
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.eventq_no = EVENTQ_0,
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},
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{
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.tx_dma_offset = 0x400,
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.rx_dma_offset = 0,
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.op_mode = DAVINCI_MCASP_DIT_MODE,
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.num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
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.tdm_slots = 32,
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.serial_dir = dm646x_dit_serializer_direction,
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.eventq_no = EVENTQ_0,
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},
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};
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static struct i2c_client *cpld_client;
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static int cpld_video_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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cpld_client = client;
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return 0;
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}
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static int __devexit cpld_video_remove(struct i2c_client *client)
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{
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cpld_client = NULL;
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return 0;
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}
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static const struct i2c_device_id cpld_video_id[] = {
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{ "cpld_video", 0 },
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{ }
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};
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static struct i2c_driver cpld_video_driver = {
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.driver = {
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.name = "cpld_video",
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},
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.probe = cpld_video_probe,
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.remove = cpld_video_remove,
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.id_table = cpld_video_id,
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};
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static void evm_init_cpld(void)
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{
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i2c_add_driver(&cpld_video_driver);
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}
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static struct i2c_board_info __initdata i2c_info[] = {
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{
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I2C_BOARD_INFO("24c256", 0x50),
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.platform_data = &eeprom_info,
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},
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{
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I2C_BOARD_INFO("pcf8574a", 0x38),
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.platform_data = &pcf_data,
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},
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{
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I2C_BOARD_INFO("cpld_reg0", 0x3a),
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},
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{
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I2C_BOARD_INFO("tlv320aic33", 0x18),
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},
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{
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I2C_BOARD_INFO("cpld_video", 0x3b),
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},
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{
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I2C_BOARD_INFO("cdce949", 0x6c),
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},
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};
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static struct davinci_i2c_platform_data i2c_pdata = {
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.bus_freq = 100 /* kHz */,
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.bus_delay = 0 /* usec */,
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};
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#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
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#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
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#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
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#define VCH2CLK_SYSCLK8 (BIT(9))
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#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
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#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
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#define VCH3CLK_SYSCLK8 (BIT(13))
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#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
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#define VIDCH2CLK (BIT(10))
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#define VIDCH3CLK (BIT(11))
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#define VIDCH1CLK (BIT(4))
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#define TVP7002_INPUT (BIT(4))
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#define TVP5147_INPUT (~BIT(4))
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#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
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#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
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#define TVP5147_CH0 "tvp514x-0"
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#define TVP5147_CH1 "tvp514x-1"
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static void __iomem *vpif_vidclkctl_reg;
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static void __iomem *vpif_vsclkdis_reg;
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/* spin lock for updating above registers */
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static spinlock_t vpif_reg_lock;
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static int set_vpif_clock(int mux_mode, int hd)
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{
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unsigned long flags;
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unsigned int value;
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int val = 0;
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int err = 0;
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if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
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return -ENXIO;
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/* disable the clock */
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spin_lock_irqsave(&vpif_reg_lock, flags);
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value = __raw_readl(vpif_vsclkdis_reg);
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value |= (VIDCH3CLK | VIDCH2CLK);
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__raw_writel(value, vpif_vsclkdis_reg);
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spin_unlock_irqrestore(&vpif_reg_lock, flags);
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val = i2c_smbus_read_byte(cpld_client);
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if (val < 0)
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return val;
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if (mux_mode == 1)
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val &= ~0x40;
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else
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val |= 0x40;
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err = i2c_smbus_write_byte(cpld_client, val);
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if (err)
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return err;
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value = __raw_readl(vpif_vidclkctl_reg);
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value &= ~(VCH2CLK_MASK);
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value &= ~(VCH3CLK_MASK);
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if (hd >= 1)
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value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
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else
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value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
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__raw_writel(value, vpif_vidclkctl_reg);
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spin_lock_irqsave(&vpif_reg_lock, flags);
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value = __raw_readl(vpif_vsclkdis_reg);
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/* enable the clock */
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value &= ~(VIDCH3CLK | VIDCH2CLK);
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__raw_writel(value, vpif_vsclkdis_reg);
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spin_unlock_irqrestore(&vpif_reg_lock, flags);
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return 0;
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}
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static struct vpif_subdev_info dm646x_vpif_subdev[] = {
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{
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.name = "adv7343",
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.board_info = {
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I2C_BOARD_INFO("adv7343", 0x2a),
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},
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},
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{
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.name = "ths7303",
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.board_info = {
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I2C_BOARD_INFO("ths7303", 0x2c),
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},
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},
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};
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static const char *output[] = {
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"Composite",
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"Component",
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"S-Video",
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};
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static struct vpif_display_config dm646x_vpif_display_config = {
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.set_clock = set_vpif_clock,
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.subdevinfo = dm646x_vpif_subdev,
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.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
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.output = output,
|
|
.output_count = ARRAY_SIZE(output),
|
|
.card_name = "DM646x EVM",
|
|
};
|
|
|
|
/**
|
|
* setup_vpif_input_path()
|
|
* @channel: channel id (0 - CH0, 1 - CH1)
|
|
* @sub_dev_name: ptr sub device name
|
|
*
|
|
* This will set vpif input to capture data from tvp514x or
|
|
* tvp7002.
|
|
*/
|
|
static int setup_vpif_input_path(int channel, const char *sub_dev_name)
|
|
{
|
|
int err = 0;
|
|
int val;
|
|
|
|
/* for channel 1, we don't do anything */
|
|
if (channel != 0)
|
|
return 0;
|
|
|
|
if (!cpld_client)
|
|
return -ENXIO;
|
|
|
|
val = i2c_smbus_read_byte(cpld_client);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
if (!strcmp(sub_dev_name, TVP5147_CH0) ||
|
|
!strcmp(sub_dev_name, TVP5147_CH1))
|
|
val &= TVP5147_INPUT;
|
|
else
|
|
val |= TVP7002_INPUT;
|
|
|
|
err = i2c_smbus_write_byte(cpld_client, val);
|
|
if (err)
|
|
return err;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* setup_vpif_input_channel_mode()
|
|
* @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
|
|
*
|
|
* This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
|
|
*/
|
|
static int setup_vpif_input_channel_mode(int mux_mode)
|
|
{
|
|
unsigned long flags;
|
|
int err = 0;
|
|
int val;
|
|
u32 value;
|
|
|
|
if (!vpif_vsclkdis_reg || !cpld_client)
|
|
return -ENXIO;
|
|
|
|
val = i2c_smbus_read_byte(cpld_client);
|
|
if (val < 0)
|
|
return val;
|
|
|
|
spin_lock_irqsave(&vpif_reg_lock, flags);
|
|
value = __raw_readl(vpif_vsclkdis_reg);
|
|
if (mux_mode) {
|
|
val &= VPIF_INPUT_TWO_CHANNEL;
|
|
value |= VIDCH1CLK;
|
|
} else {
|
|
val |= VPIF_INPUT_ONE_CHANNEL;
|
|
value &= ~VIDCH1CLK;
|
|
}
|
|
__raw_writel(value, vpif_vsclkdis_reg);
|
|
spin_unlock_irqrestore(&vpif_reg_lock, flags);
|
|
|
|
err = i2c_smbus_write_byte(cpld_client, val);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct tvp514x_platform_data tvp5146_pdata = {
|
|
.clk_polarity = 0,
|
|
.hs_polarity = 1,
|
|
.vs_polarity = 1
|
|
};
|
|
|
|
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
|
|
|
|
static struct vpif_subdev_info vpif_capture_sdev_info[] = {
|
|
{
|
|
.name = TVP5147_CH0,
|
|
.board_info = {
|
|
I2C_BOARD_INFO("tvp5146", 0x5d),
|
|
.platform_data = &tvp5146_pdata,
|
|
},
|
|
.input = INPUT_CVBS_VI2B,
|
|
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
|
.can_route = 1,
|
|
.vpif_if = {
|
|
.if_type = VPIF_IF_BT656,
|
|
.hd_pol = 1,
|
|
.vd_pol = 1,
|
|
.fid_pol = 0,
|
|
},
|
|
},
|
|
{
|
|
.name = TVP5147_CH1,
|
|
.board_info = {
|
|
I2C_BOARD_INFO("tvp5146", 0x5c),
|
|
.platform_data = &tvp5146_pdata,
|
|
},
|
|
.input = INPUT_SVIDEO_VI2C_VI1C,
|
|
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
|
.can_route = 1,
|
|
.vpif_if = {
|
|
.if_type = VPIF_IF_BT656,
|
|
.hd_pol = 1,
|
|
.vd_pol = 1,
|
|
.fid_pol = 0,
|
|
},
|
|
},
|
|
};
|
|
|
|
static const struct vpif_input dm6467_ch0_inputs[] = {
|
|
{
|
|
.input = {
|
|
.index = 0,
|
|
.name = "Composite",
|
|
.type = V4L2_INPUT_TYPE_CAMERA,
|
|
.std = TVP514X_STD_ALL,
|
|
},
|
|
.subdev_name = TVP5147_CH0,
|
|
},
|
|
};
|
|
|
|
static const struct vpif_input dm6467_ch1_inputs[] = {
|
|
{
|
|
.input = {
|
|
.index = 0,
|
|
.name = "S-Video",
|
|
.type = V4L2_INPUT_TYPE_CAMERA,
|
|
.std = TVP514X_STD_ALL,
|
|
},
|
|
.subdev_name = TVP5147_CH1,
|
|
},
|
|
};
|
|
|
|
static struct vpif_capture_config dm646x_vpif_capture_cfg = {
|
|
.setup_input_path = setup_vpif_input_path,
|
|
.setup_input_channel_mode = setup_vpif_input_channel_mode,
|
|
.subdev_info = vpif_capture_sdev_info,
|
|
.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
|
|
.chan_config[0] = {
|
|
.inputs = dm6467_ch0_inputs,
|
|
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
|
|
},
|
|
.chan_config[1] = {
|
|
.inputs = dm6467_ch1_inputs,
|
|
.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
|
|
},
|
|
};
|
|
|
|
static void __init evm_init_video(void)
|
|
{
|
|
vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
|
|
vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
|
|
if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
|
|
pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
|
|
return;
|
|
}
|
|
spin_lock_init(&vpif_reg_lock);
|
|
|
|
dm646x_setup_vpif(&dm646x_vpif_display_config,
|
|
&dm646x_vpif_capture_cfg);
|
|
}
|
|
|
|
static void __init evm_init_i2c(void)
|
|
{
|
|
davinci_init_i2c(&i2c_pdata);
|
|
i2c_add_driver(&dm6467evm_cpld_driver);
|
|
i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
|
|
evm_init_cpld();
|
|
evm_init_video();
|
|
}
|
|
|
|
#define CDCE949_XIN_RATE 27000000
|
|
|
|
/* CDCE949 support - "lpsc" field is overridden to work as clock number */
|
|
static struct clk cdce_clk_in = {
|
|
.name = "cdce_xin",
|
|
.rate = CDCE949_XIN_RATE,
|
|
};
|
|
|
|
static struct clk_lookup cdce_clks[] = {
|
|
CLK(NULL, "xin", &cdce_clk_in),
|
|
CLK(NULL, NULL, NULL),
|
|
};
|
|
|
|
static void __init cdce_clk_init(void)
|
|
{
|
|
struct clk_lookup *c;
|
|
struct clk *clk;
|
|
|
|
for (c = cdce_clks; c->clk; c++) {
|
|
clk = c->clk;
|
|
clkdev_add(c);
|
|
clk_register(clk);
|
|
}
|
|
}
|
|
|
|
static void __init davinci_map_io(void)
|
|
{
|
|
dm646x_init();
|
|
cdce_clk_init();
|
|
}
|
|
|
|
static struct davinci_uart_config uart_config __initdata = {
|
|
.enabled_uarts = (1 << 0),
|
|
};
|
|
|
|
#define DM646X_EVM_PHY_MASK (0x2)
|
|
#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
|
|
|
|
static __init void evm_init(void)
|
|
{
|
|
struct davinci_soc_info *soc_info = &davinci_soc_info;
|
|
|
|
evm_init_i2c();
|
|
davinci_serial_init(&uart_config);
|
|
dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
|
|
dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
|
|
|
|
platform_device_register(&davinci_nand_device);
|
|
|
|
if (HAS_ATA)
|
|
davinci_init_ide();
|
|
|
|
soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK;
|
|
soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY;
|
|
}
|
|
|
|
static __init void davinci_dm646x_evm_irq_init(void)
|
|
{
|
|
davinci_irq_init();
|
|
}
|
|
|
|
#define DM646X_EVM_REF_FREQ 27000000
|
|
#define DM6467T_EVM_REF_FREQ 33000000
|
|
|
|
void __init dm646x_board_setup_refclk(struct clk *clk)
|
|
{
|
|
if (machine_is_davinci_dm6467tevm())
|
|
clk->rate = DM6467T_EVM_REF_FREQ;
|
|
else
|
|
clk->rate = DM646X_EVM_REF_FREQ;
|
|
}
|
|
|
|
MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
|
|
.phys_io = IO_PHYS,
|
|
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
|
|
.boot_params = (0x80000100),
|
|
.map_io = davinci_map_io,
|
|
.init_irq = davinci_dm646x_evm_irq_init,
|
|
.timer = &davinci_timer,
|
|
.init_machine = evm_init,
|
|
MACHINE_END
|
|
|
|
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
|
|
.phys_io = IO_PHYS,
|
|
.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
|
|
.boot_params = (0x80000100),
|
|
.map_io = davinci_map_io,
|
|
.init_irq = davinci_dm646x_evm_irq_init,
|
|
.timer = &davinci_timer,
|
|
.init_machine = evm_init,
|
|
MACHINE_END
|
|
|