0f18597195
This patch adds support for the Gateworks Avila Network Platform in a separate set of setup files to the IXDP425. This is necessary now that a driver for the Avila CF card slot is available. It also adds support for a minor variant on the Avila board known as the Loft, which has a different number of maximum PCI devices. Signed-off-by: Michael-Luke Jones <mlj28@cam.ac.uk> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
162 lines
4.6 KiB
Plaintext
162 lines
4.6 KiB
Plaintext
if ARCH_IXP4XX
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config ARCH_SUPPORTS_BIG_ENDIAN
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bool
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default y
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menu "Intel IXP4xx Implementation Options"
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comment "IXP4xx Platforms"
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config MACH_NSLU2
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bool
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prompt "Linksys NSLU2"
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select PCI
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help
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Say 'Y' here if you want your kernel to support Linksys's
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NSLU2 NAS device. For more information on this platform,
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see http://www.nslu2-linux.org
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config MACH_AVILA
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bool "Avila"
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select PCI
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help
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Say 'Y' here if you want your kernel to support the Gateworks
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Avila Network Platform. For more information on this platform,
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see <file:Documentation/arm/IXP4xx>.
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config MACH_LOFT
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bool "Loft"
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depends on MACH_AVILA
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help
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Say 'Y' here if you want your kernel to support the Giant
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Shoulder Inc Loft board (a minor variation on the standard
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Gateworks Avila Network Platform).
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config ARCH_ADI_COYOTE
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bool "Coyote"
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select PCI
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help
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Say 'Y' here if you want your kernel to support the ADI
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Engineering Coyote Gateway Reference Platform. For more
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information on this platform, see <file:Documentation/arm/IXP4xx>.
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config ARCH_IXDP425
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bool "IXDP425"
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help
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Say 'Y' here if you want your kernel to support Intel's
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IXDP425 Development Platform (Also known as Richfield).
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For more information on this platform, see <file:Documentation/arm/IXP4xx>.
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config MACH_IXDPG425
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bool "IXDPG425"
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help
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Say 'Y' here if you want your kernel to support Intel's
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IXDPG425 Development Platform (Also known as Montajade).
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For more information on this platform, see <file:Documentation/arm/IXP4xx>.
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config MACH_IXDP465
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bool "IXDP465"
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help
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Say 'Y' here if you want your kernel to support Intel's
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IXDP465 Development Platform (Also known as BMP).
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For more information on this platform, see <file:Documentation/arm/IXP4xx>.
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#
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# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
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# number from the bootloader due to marketing monkeys, so we just enable it
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# by default if IXDP425 is enabled.
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#
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config ARCH_IXCDP1100
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bool
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depends on ARCH_IXDP425
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default y
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config ARCH_PRPMC1100
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bool "PrPMC1100"
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help
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Say 'Y' here if you want your kernel to support the Motorola
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PrPCM1100 Processor Mezanine Module. For more information on
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this platform, see <file:Documentation/arm/IXP4xx>.
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config MACH_NAS100D
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bool
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prompt "NAS100D"
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select PCI
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help
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Say 'Y' here if you want your kernel to support Iomega's
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NAS 100d device. For more information on this platform,
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see http://www.nslu2-linux.org/wiki/NAS100d/HomePage
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#
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# Avila and IXDP share the same source for now. Will change in future
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#
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config ARCH_IXDP4XX
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bool
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depends on ARCH_IXDP425 || MACH_IXDP465
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default y
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#
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# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
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#
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config CPU_IXP46X
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bool
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depends on MACH_IXDP465
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default y
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config MACH_GTWX5715
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bool "Gemtek WX5715 (Linksys WRV54G)"
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depends on ARCH_IXP4XX
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select PCI
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help
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This board is currently inside the Linksys WRV54G Gateways.
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IXP425 - 266mhz
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32mb SDRAM
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8mb Flash
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miniPCI slot 0 does not have a card connector soldered to the board
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miniPCI slot 1 has an ISL3880 802.11g card (Prism54)
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npe0 is connected to a Kendin KS8995M Switch (4 ports)
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npe1 is the "wan" port
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"Console" UART is available on J11 as console
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"High Speed" UART is n/c (as far as I can tell)
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20 Pin ARM/Xscale JTAG interface on J2
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comment "IXP4xx Options"
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config DMABOUNCE
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bool
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default y
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depends on PCI
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config IXP4XX_INDIRECT_PCI
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bool "Use indirect PCI memory access"
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depends on PCI
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help
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IXP4xx provides two methods of accessing PCI memory space:
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1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
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To access PCI via this space, we simply ioremap() the BAR
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into the kernel and we can use the standard read[bwl]/write[bwl]
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macros. This is the preferred method due to speed but it
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limits the system to just 64MB of PCI memory. This can be
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problematic if using video cards and other memory-heavy devices.
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2) If > 64MB of memory space is required, the IXP4xx can be
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configured to use indirect registers to access PCI This allows
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for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
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The disadvantage of this is that every PCI access requires
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three local register accesses plus a spinlock, but in some
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cases the performance hit is acceptable. In addition, you cannot
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mmap() PCI devices in this case due to the indirect nature
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of the PCI window.
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By default, the direct method is used. Choose this option if you
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need to use the indirect method instead. If you don't know
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what you need, leave this option unselected.
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endmenu
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endif
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