2d4dc890b5
Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov <isloginov@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Peter Horton <phorton@bitbox.co.uk> Cc: "Ed L. Cashin" <ecashin@coraid.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
118 lines
4.3 KiB
C
118 lines
4.3 KiB
C
/* MN10300 Cache flushing
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_CACHEFLUSH_H
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#define _ASM_CACHEFLUSH_H
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#ifndef __ASSEMBLY__
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/* Keep includes the same across arches. */
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#include <linux/mm.h>
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/*
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* virtually-indexed cache management (our cache is physically indexed)
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*/
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#define flush_cache_all() do {} while (0)
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#define flush_cache_mm(mm) do {} while (0)
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#define flush_cache_dup_mm(mm) do {} while (0)
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#define flush_cache_range(mm, start, end) do {} while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
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#define flush_cache_vmap(start, end) do {} while (0)
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#define flush_cache_vunmap(start, end) do {} while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do {} while (0)
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#define flush_dcache_mmap_lock(mapping) do {} while (0)
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#define flush_dcache_mmap_unlock(mapping) do {} while (0)
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/*
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* physically-indexed cache management
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*/
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#ifndef CONFIG_MN10300_CACHE_DISABLED
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
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#else
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#define flush_icache_range(start, end) do {} while (0)
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#define flush_icache_page(vma, pg) do {} while (0)
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#endif
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#define flush_icache_user_range(vma, pg, adr, len) \
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flush_icache_range(adr, adr + len)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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flush_icache_page(vma, page); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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/*
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* primitive routines
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*/
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#ifndef CONFIG_MN10300_CACHE_DISABLED
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extern void mn10300_icache_inv(void);
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extern void mn10300_dcache_inv(void);
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extern void mn10300_dcache_inv_page(unsigned start);
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extern void mn10300_dcache_inv_range(unsigned start, unsigned end);
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extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);
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#ifdef CONFIG_MN10300_CACHE_WBACK
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extern void mn10300_dcache_flush(void);
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extern void mn10300_dcache_flush_page(unsigned start);
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extern void mn10300_dcache_flush_range(unsigned start, unsigned end);
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extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);
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extern void mn10300_dcache_flush_inv(void);
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extern void mn10300_dcache_flush_inv_page(unsigned start);
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extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);
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extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);
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#else
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#define mn10300_dcache_flush() do {} while (0)
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#define mn10300_dcache_flush_page(start) do {} while (0)
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#define mn10300_dcache_flush_range(start, end) do {} while (0)
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#define mn10300_dcache_flush_range2(start, size) do {} while (0)
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#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
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#define mn10300_dcache_flush_inv_page(start) \
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mn10300_dcache_inv_page((start))
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#define mn10300_dcache_flush_inv_range(start, end) \
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mn10300_dcache_inv_range((start), (end))
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#define mn10300_dcache_flush_inv_range2(start, size) \
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mn10300_dcache_inv_range2((start), (size))
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#endif /* CONFIG_MN10300_CACHE_WBACK */
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#else
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#define mn10300_icache_inv() do {} while (0)
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#define mn10300_dcache_inv() do {} while (0)
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#define mn10300_dcache_inv_page(start) do {} while (0)
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#define mn10300_dcache_inv_range(start, end) do {} while (0)
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#define mn10300_dcache_inv_range2(start, size) do {} while (0)
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#define mn10300_dcache_flush() do {} while (0)
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#define mn10300_dcache_flush_inv_page(start) do {} while (0)
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#define mn10300_dcache_flush_inv() do {} while (0)
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#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
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#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
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#define mn10300_dcache_flush_page(start) do {} while (0)
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#define mn10300_dcache_flush_range(start, end) do {} while (0)
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#define mn10300_dcache_flush_range2(start, size) do {} while (0)
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#endif /* CONFIG_MN10300_CACHE_DISABLED */
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/*
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* internal debugging function
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*/
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#ifdef CONFIG_DEBUG_PAGEALLOC
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extern void kernel_map_pages(struct page *page, int numpages, int enable);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_CACHEFLUSH_H */
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