531b617c71
This patch moves items of the s3c24xx support into a new plat-s3c directory for items that use the s3c24xx support but are not directly s3c24xx compatible, such as the s3c2400 and s3c6400. git mv commands: git mv include/asm-arm/arch-s3c2410/iic.h include/asm-arm/plat-s3c/iic.h git mv include/asm-arm/arch-s3c2410/nand.h include/asm-arm/plat-s3c/nand.h git mv include/asm-arm/arch-s3c2410/regs-iic.h include/asm-arm/plat-s3c/regs-iic.h git mv include/asm-arm/arch-s3c2410/regs-nand.h include/asm-arm/plat-s3c/regs-nand.h git mv include/asm-arm/arch-s3c2410/regs-rtc.h include/asm-arm/plat-s3c/regs-rtc.h git mv include/asm-arm/arch-s3c2410/regs-serial.h include/asm-arm/plat-s3c/regs-serial.h git mv include/asm-arm/arch-s3c2410/regs-timer.h include/asm-arm/plat-s3c/regs-timer.h git mv include/asm-arm/arch-s3c2410/regs-watchdog.h include/asm-arm/plat-s3c/regs-watchdog.h Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
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*
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* Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 NAND register definitions
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*/
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#ifndef __ASM_ARM_REGS_NAND
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#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
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#define S3C2410_NFREG(x) (x)
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#define S3C2410_NFCONF S3C2410_NFREG(0x00)
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#define S3C2410_NFCMD S3C2410_NFREG(0x04)
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#define S3C2410_NFADDR S3C2410_NFREG(0x08)
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#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
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#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
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#define S3C2410_NFECC S3C2410_NFREG(0x14)
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#define S3C2440_NFCONT S3C2410_NFREG(0x04)
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#define S3C2440_NFCMD S3C2410_NFREG(0x08)
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#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
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#define S3C2440_NFDATA S3C2410_NFREG(0x10)
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#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
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#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
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#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
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#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
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#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
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#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
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#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
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#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
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#define S3C2440_NFSECC S3C24E10_NFREG(0x34)
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#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
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#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
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#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
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#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
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#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
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#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
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#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
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#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
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#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
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#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
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#define S3C2410_NFCONF_INITECC (1<<12)
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#define S3C2410_NFCONF_nFCE (1<<11)
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#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
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#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
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#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
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#define S3C2410_NFSTAT_BUSY (1<<0)
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#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
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#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
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#define S3C2440_NFCONF_ADVFLASH (1<<3)
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#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
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#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
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#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
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#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
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#define S3C2440_NFCONT_SOFTLOCK (1<<12)
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#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
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#define S3C2440_NFCONT_RNBINT_EN (1<<9)
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#define S3C2440_NFCONT_RN_FALLING (1<<8)
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#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
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#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
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#define S3C2440_NFCONT_INITECC (1<<4)
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#define S3C2440_NFCONT_nFCE (1<<1)
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#define S3C2440_NFCONT_ENABLE (1<<0)
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#define S3C2440_NFSTAT_READY (1<<0)
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#define S3C2440_NFSTAT_nCE (1<<1)
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#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
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#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
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#define S3C2412_NFCONF_NANDBOOT (1<<31)
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#define S3C2412_NFCONF_ECCCLKCON (1<<30)
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#define S3C2412_NFCONF_ECC_MLC (1<<24)
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#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
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#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
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#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
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#define S3C2412_NFCONT_SOFTLOCK (1<<16)
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#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
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#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
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#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
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#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
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#define S3C2412_NFCONT_nFCE1 (1<<2)
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#define S3C2412_NFCONT_nFCE0 (1<<1)
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#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
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#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
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#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
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#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
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#define S3C2412_NFSTAT_nFCE1 (1<<3)
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#define S3C2412_NFSTAT_nFCE0 (1<<2)
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#define S3C2412_NFSTAT_Res1 (1<<1)
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#define S3C2412_NFSTAT_READY (1<<0)
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#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
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#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
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#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
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#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
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#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
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#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
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#define S3C2412_NFECCERR_NONE (0)
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#define S3C2412_NFECCERR_1BIT (1)
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#define S3C2412_NFECCERR_MULTIBIT (2)
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#define S3C2412_NFECCERR_ECCAREA (3)
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#endif /* __ASM_ARM_REGS_NAND */
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