1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/*
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* arch/sh/kernel/cpu/sh4/probe.c
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*
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* CPU Subtype Probing for SH-4.
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*
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* Copyright (C) 2001, 2002, 2003, 2004 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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int __init detect_cpu_and_cache_system(void)
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{
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unsigned long pvr, prr, cvr;
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unsigned long size;
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static unsigned long sizes[16] = {
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[1] = (1 << 12),
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[2] = (1 << 13),
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[4] = (1 << 14),
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[8] = (1 << 15),
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[9] = (1 << 16)
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};
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pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
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prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
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cvr = (ctrl_inl(CCN_CVR));
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/*
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* Setup some sane SH-4 defaults for the icache
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*/
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cpu_data->icache.way_incr = (1 << 13);
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cpu_data->icache.entry_shift = 5;
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cpu_data->icache.entry_mask = 0x1fe0;
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cpu_data->icache.sets = 256;
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cpu_data->icache.ways = 1;
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cpu_data->icache.linesz = L1_CACHE_BYTES;
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/*
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* And again for the dcache ..
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*/
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cpu_data->dcache.way_incr = (1 << 14);
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cpu_data->dcache.entry_shift = 5;
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cpu_data->dcache.entry_mask = 0x3fe0;
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cpu_data->dcache.sets = 512;
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cpu_data->dcache.ways = 1;
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cpu_data->dcache.linesz = L1_CACHE_BYTES;
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/* Set the FPU flag, virtually all SH-4's have one */
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cpu_data->flags |= CPU_HAS_FPU;
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/*
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* Probe the underlying processor version/revision and
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* adjust cpu_data setup accordingly.
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*/
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switch (pvr) {
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case 0x205:
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cpu_data->type = CPU_SH7750;
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cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
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break;
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case 0x206:
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cpu_data->type = CPU_SH7750S;
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cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER;
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break;
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case 0x1100:
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cpu_data->type = CPU_SH7751;
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break;
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case 0x2000:
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cpu_data->type = CPU_SH73180;
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cpu_data->icache.ways = 4;
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cpu_data->dcache.ways = 4;
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cpu_data->flags &= ~CPU_HAS_FPU;
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break;
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case 0x8000:
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cpu_data->type = CPU_ST40RA;
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break;
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case 0x8100:
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cpu_data->type = CPU_ST40GX1;
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break;
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case 0x700:
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cpu_data->type = CPU_SH4_501;
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cpu_data->icache.ways = 2;
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cpu_data->dcache.ways = 2;
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/* No FPU on the SH4-500 series.. */
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cpu_data->flags &= ~CPU_HAS_FPU;
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break;
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case 0x600:
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cpu_data->type = CPU_SH4_202;
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cpu_data->icache.ways = 2;
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cpu_data->dcache.ways = 2;
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break;
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case 0x500 ... 0x501:
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switch (prr) {
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case 0x10: cpu_data->type = CPU_SH7750R; break;
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case 0x11: cpu_data->type = CPU_SH7751R; break;
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case 0x50: cpu_data->type = CPU_SH7760; break;
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}
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cpu_data->icache.ways = 2;
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cpu_data->dcache.ways = 2;
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break;
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default:
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cpu_data->type = CPU_SH_NONE;
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break;
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}
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/*
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* On anything that's not a direct-mapped cache, look to the CVR
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* for I/D-cache specifics.
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*/
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if (cpu_data->icache.ways > 1) {
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size = sizes[(cvr >> 20) & 0xf];
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cpu_data->icache.way_incr = (size >> 1);
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cpu_data->icache.sets = (size >> 6);
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cpu_data->icache.entry_mask =
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(cpu_data->icache.way_incr - (1 << 5));
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}
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if (cpu_data->dcache.ways > 1) {
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size = sizes[(cvr >> 16) & 0xf];
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cpu_data->dcache.way_incr = (size >> 1);
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cpu_data->dcache.sets = (size >> 6);
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cpu_data->dcache.entry_mask =
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(cpu_data->dcache.way_incr - (1 << 5));
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}
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return 0;
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}
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