49cbe78637
"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/*
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* linux/arch/arm/mach-mmp/irq.c
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*
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* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
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*
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* Author: Bin Yang <bin.yang@marvell.com>
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* Created: Sep 30, 2008
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* Copyright: Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/regs-icu.h>
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#include "common.h"
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#define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
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#define PRIORITY_DEFAULT 0x1
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#define PRIORITY_NONE 0x0 /* means IRQ disabled */
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static void icu_mask_irq(unsigned int irq)
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{
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__raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq));
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}
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static void icu_unmask_irq(unsigned int irq)
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{
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__raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq));
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}
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static struct irq_chip icu_irq_chip = {
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.name = "icu_irq",
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.ack = icu_mask_irq,
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.mask = icu_mask_irq,
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.unmask = icu_unmask_irq,
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};
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void __init icu_init_irq(void)
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{
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int irq;
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for (irq = 0; irq < 64; irq++) {
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icu_mask_irq(irq);
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set_irq_chip(irq, &icu_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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