fd8e7af8d0
The PXA manuals indicate that when in standby or sleep modes, clocks to peripherals are shut off by the processor itself. Eg: PXA270 standby: "In standby mode, all clocks are disabled except those for the power manager and the RTC." PXA270 sleep: "In sleep mode, all clocks are disabled to the processor and to all peripherals except the RTC." PXA255 sleep: "In Sleep Mode, all processor and peripheral clocks are disabled, except the RTC." Therefore, it should be safe to leave the clock enable register alone prior to entering low power modes for these SoCs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
423 lines
10 KiB
C
423 lines
10 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa27x.c
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*
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* Author: Nicolas Pitre
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* Created: Nov 05, 2002
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA27x aka Bulverde.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/platform_device.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-regs.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M, n2, N, S;
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int cccr_a, t, ht, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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n2 = (ccsr>>7) & 0xf;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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N = (L * n2) / 2;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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S = (b) ? L : (L/2);
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if (info) {
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
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(t) ? "" : "in" );
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printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
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S / 1000000, (S % 1000000) / 10000 );
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}
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return (t) ? (N/1000) : (L/1000);
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}
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/*
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* Return the current mem clock frequency in units of 10kHz as
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* reflected by CCCR[A], B, and L
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*/
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unsigned int pxa27x_get_memclk_frequency_10khz(void)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M;
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int cccr_a, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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return (M / 10000);
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}
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/*
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* Return the current LCD clock frequency in units of 10kHz as
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*/
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static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
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{
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unsigned long ccsr;
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unsigned int l, L, k, K;
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ccsr = CCSR;
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l = ccsr & 0x1f;
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k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
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L = l * BASE_CLK;
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K = L / k;
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return (K / 10000);
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}
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static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
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{
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return pxa27x_get_lcdclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa27x_lcd_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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.getrate = clk_pxa27x_lcd_getrate,
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};
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static struct clk pxa27x_clks[] = {
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INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
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INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
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INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
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INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
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INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
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INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
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INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
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INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
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INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
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INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
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INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
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INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
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INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
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INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
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/*
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INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
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INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
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INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
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INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
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INIT_CKEN("IMCLK", IM, 0, 0, NULL),
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INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
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*/
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};
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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#define RESTORE_GPLEVEL(n) do { \
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GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
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GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
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} while (0)
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
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SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
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SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
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SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
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SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
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SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
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SLEEP_SAVE_SIZE
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};
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void pxa27x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
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SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
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SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
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SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(GAFR3_L); SAVE(GAFR3_U);
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SAVE(MDREFR);
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SAVE(PWER); SAVE(PCFR); SAVE(PRER);
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SAVE(PFER); SAVE(PKWR);
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SAVE(ICMR); ICMR = 0;
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SAVE(CKEN);
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SAVE(PSTR);
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/* Clear GPIO transition detect bits */
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GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
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}
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void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
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{
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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/* restore registers */
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RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
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RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
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RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(GAFR3_L); RESTORE(GAFR3_U);
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RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
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RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
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RESTORE(MDREFR);
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RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
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RESTORE(PFER); RESTORE(PKWR);
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PSSR = PSSR_RDH | PSSR_PH;
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RESTORE(CKEN);
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ICLR = 0;
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ICCR = 1;
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RESTORE(ICMR);
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RESTORE(PSTR);
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}
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void pxa27x_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_standby(void);
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/* ensure voltage-change sequencer not initiated, which hangs */
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PCFR &= ~PCFR_FVC;
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/* Clear edge-detect status register. */
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PEDR = 0xDF12FE1B;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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pxa_cpu_standby();
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break;
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa27x_cpu_suspend(PWRMODE_SLEEP);
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break;
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}
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}
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static int pxa27x_cpu_pm_valid(suspend_state_t state)
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{
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return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
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}
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static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
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.save_size = SLEEP_SAVE_SIZE,
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.save = pxa27x_cpu_pm_save,
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.restore = pxa27x_cpu_pm_restore,
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.valid = pxa27x_cpu_pm_valid,
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.enter = pxa27x_cpu_pm_enter,
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};
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static void __init pxa27x_init_pm(void)
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{
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pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
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}
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#else
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static inline void pxa27x_init_pm(void) {}
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#endif
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/* PXA27x: Various gpios can issue wakeup events. This logic only
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* handles the simple cases, not the WEMUX2 and WEMUX3 options
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*/
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#define PXA27x_GPIO_NOWAKE_MASK \
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((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
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#define WAKEMASK(gpio) \
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(((gpio) <= 15) \
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? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
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: ((gpio == 35) ? (1 << 24) : 0))
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static int pxa27x_set_wake(unsigned int irq, unsigned int on)
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{
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int gpio = IRQ_TO_GPIO(irq);
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uint32_t mask;
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if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
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if (WAKEMASK(gpio) == 0)
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return -EINVAL;
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mask = WAKEMASK(gpio);
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if (on) {
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if (GRER(gpio) | GPIO_bit(gpio))
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PRER |= mask;
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else
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PRER &= ~mask;
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if (GFER(gpio) | GPIO_bit(gpio))
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PFER |= mask;
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else
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PFER &= ~mask;
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}
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goto set_pwer;
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}
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switch (irq) {
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case IRQ_RTCAlrm:
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mask = PWER_RTC;
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break;
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case IRQ_USB:
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mask = 1u << 26;
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break;
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default:
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return -EINVAL;
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}
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set_pwer:
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if (on)
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PWER |= mask;
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else
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PWER &=~mask;
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return 0;
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}
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void __init pxa27x_init_irq(void)
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{
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pxa_init_irq_low();
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pxa_init_irq_high();
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pxa_init_irq_gpio(128);
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pxa_init_irq_set_wake(pxa27x_set_wake);
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}
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/*
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* device registration specific to PXA27x.
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*/
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static struct resource i2c_power_resources[] = {
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{
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.start = 0x40f00180,
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.end = 0x40f001a3,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_PWRI2C,
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.end = IRQ_PWRI2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device pxa27x_device_i2c_power = {
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.name = "pxa2xx-i2c",
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.id = 1,
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.resource = i2c_power_resources,
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.num_resources = ARRAY_SIZE(i2c_power_resources),
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};
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static struct platform_device *devices[] __initdata = {
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&pxa_device_udc,
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&pxa_device_ffuart,
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&pxa_device_btuart,
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&pxa_device_stuart,
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&pxa_device_i2s,
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&pxa_device_rtc,
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&pxa27x_device_i2c_power,
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&pxa27x_device_ssp1,
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&pxa27x_device_ssp2,
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&pxa27x_device_ssp3,
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};
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static int __init pxa27x_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa27x()) {
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clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
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if ((ret = pxa_init_dma(32)))
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return ret;
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pxa27x_init_pm();
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ret = platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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return ret;
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}
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subsys_initcall(pxa27x_init);
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