385 lines
12 KiB
C
385 lines
12 KiB
C
/*
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* Version 2.24
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*
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* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
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* IDE driver for Linux.
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*
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* Copyright (c) 2000-2002 Vojtech Pavlik
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* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
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*
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* Based on the work of:
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* Andre Hedrick
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*/
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#include "ide-timing.h"
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#define AMD_IDE_CONFIG (0x01 + amd_config->base)
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#define AMD_CABLE_DETECT (0x02 + amd_config->base)
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#define AMD_DRIVE_TIMING (0x08 + amd_config->base)
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#define AMD_8BIT_TIMING (0x0e + amd_config->base)
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#define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
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#define AMD_UDMA_TIMING (0x10 + amd_config->base)
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#define AMD_CHECK_SWDMA 0x08
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#define AMD_BAD_SWDMA 0x10
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#define AMD_BAD_FIFO 0x20
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#define AMD_CHECK_SERENADE 0x40
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/*
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* AMD SouthBridge chips.
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*/
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static struct amd_ide_chip {
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unsigned short id;
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u8 base;
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u8 udma_mask;
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u8 flags;
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} amd_ide_chips[] = {
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{ PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, ATA_UDMA2, AMD_BAD_SWDMA },
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{ PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, ATA_UDMA4, AMD_CHECK_SWDMA },
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{ PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, ATA_UDMA5, AMD_BAD_FIFO },
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{ PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, ATA_UDMA5, },
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{ PCI_DEVICE_ID_AMD_8111_IDE, 0x40, ATA_UDMA6, AMD_CHECK_SERENADE },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, ATA_UDMA5, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE, 0x50, ATA_UDMA6, },
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{ PCI_DEVICE_ID_AMD_CS5536_IDE, 0x40, ATA_UDMA5, },
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{ 0 }
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};
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static struct amd_ide_chip *amd_config;
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static const struct ide_port_info *amd_chipset;
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static unsigned int amd_80w;
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static unsigned int amd_clock;
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static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
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static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
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/*
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* amd_set_speed() writes timing values to the chipset registers
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*/
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static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
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{
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unsigned char t;
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pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
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t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
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pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
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pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
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((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
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pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
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((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
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switch (amd_config->udma_mask) {
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case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
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case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
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case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
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case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
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default: return;
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}
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pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
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}
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/*
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* amd_set_drive() computes timing values and configures the chipset
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* to a desired transfer mode. It also can be called by upper layers.
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*/
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static void amd_set_drive(ide_drive_t *drive, const u8 speed)
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{
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ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
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struct ide_timing t, p;
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int T, UT;
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T = 1000000000 / amd_clock;
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UT = (amd_config->udma_mask == ATA_UDMA2) ? T : (T / 2);
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ide_timing_compute(drive, speed, &t, T, UT);
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if (peer->present) {
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ide_timing_compute(peer, peer->current_speed, &p, T, UT);
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ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
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}
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if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
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if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
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amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
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}
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/*
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* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
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*/
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static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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amd_set_drive(drive, XFER_PIO_0 + pio);
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}
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/*
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* The initialization callback. Here we determine the IDE chip type
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* and initialize its drive independent registers.
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*/
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static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
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{
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unsigned char t;
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unsigned int u;
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int i;
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/*
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* Check for bad SWDMA.
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*/
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if (amd_config->flags & AMD_CHECK_SWDMA) {
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if (dev->revision <= 7)
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amd_config->flags |= AMD_BAD_SWDMA;
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}
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/*
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* Check 80-wire cable presence.
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*/
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switch (amd_config->udma_mask) {
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case ATA_UDMA6:
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case ATA_UDMA5:
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pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
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pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
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amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
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for (i = 24; i >= 0; i -= 8)
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if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
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printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
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amd_chipset->name);
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amd_80w |= (1 << (1 - (i >> 4)));
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}
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break;
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case ATA_UDMA4:
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/* no host side cable detection */
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amd_80w = 0x03;
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break;
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}
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/*
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* Take care of prefetch & postwrite.
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*/
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pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
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pci_write_config_byte(dev, AMD_IDE_CONFIG,
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(amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
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/*
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* Take care of incorrectly wired Serenade mainboards.
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*/
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if ((amd_config->flags & AMD_CHECK_SERENADE) &&
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dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
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dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
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amd_config->udma_mask = ATA_UDMA5;
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/*
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* Determine the system bus clock.
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*/
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amd_clock = system_bus_clock() * 1000;
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switch (amd_clock) {
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case 33000: amd_clock = 33333; break;
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case 37000: amd_clock = 37500; break;
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case 41000: amd_clock = 41666; break;
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}
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if (amd_clock < 20000 || amd_clock > 50000) {
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printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
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amd_chipset->name, amd_clock);
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amd_clock = 33333;
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}
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/*
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* Print the boot message.
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*/
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printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
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amd_chipset->name, pci_name(dev), dev->revision,
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amd_dma[fls(amd_config->udma_mask) - 1]);
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return dev->irq;
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}
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static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
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{
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if (hwif->irq == 0) /* 0 is bogus but will do for now */
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hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
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hwif->set_pio_mode = &amd_set_pio_mode;
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hwif->set_dma_mode = &amd_set_drive;
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if (!hwif->dma_base)
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return;
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hwif->ultra_mask = amd_config->udma_mask;
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if (amd_config->flags & AMD_BAD_SWDMA)
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hwif->swdma_mask = 0x00;
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if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
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if ((amd_80w >> hwif->channel) & 1)
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hwif->cbl = ATA_CBL_PATA80;
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else
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hwif->cbl = ATA_CBL_PATA40;
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}
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}
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#define IDE_HFLAGS_AMD \
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(IDE_HFLAG_PIO_NO_BLACKLIST | \
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IDE_HFLAG_PIO_NO_DOWNGRADE | \
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IDE_HFLAG_POST_SET_MODE | \
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IDE_HFLAG_IO_32BIT | \
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IDE_HFLAG_UNMASK_IRQS | \
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IDE_HFLAG_BOOTABLE)
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#define DECLARE_AMD_DEV(name_str) \
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{ \
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.name = name_str, \
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.init_chipset = init_chipset_amd74xx, \
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.init_hwif = init_hwif_amd74xx, \
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.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
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.host_flags = IDE_HFLAGS_AMD, \
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.pio_mask = ATA_PIO5, \
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.swdma_mask = ATA_SWDMA2, \
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.mwdma_mask = ATA_MWDMA2, \
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}
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#define DECLARE_NV_DEV(name_str) \
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{ \
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.name = name_str, \
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.init_chipset = init_chipset_amd74xx, \
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.init_hwif = init_hwif_amd74xx, \
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.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
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.host_flags = IDE_HFLAGS_AMD, \
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.pio_mask = ATA_PIO5, \
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.swdma_mask = ATA_SWDMA2, \
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.mwdma_mask = ATA_MWDMA2, \
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}
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static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
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/* 0 */ DECLARE_AMD_DEV("AMD7401"),
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/* 1 */ DECLARE_AMD_DEV("AMD7409"),
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/* 2 */ DECLARE_AMD_DEV("AMD7411"),
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/* 3 */ DECLARE_AMD_DEV("AMD7441"),
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/* 4 */ DECLARE_AMD_DEV("AMD8111"),
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/* 5 */ DECLARE_NV_DEV("NFORCE"),
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/* 6 */ DECLARE_NV_DEV("NFORCE2"),
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/* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
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/* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
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/* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
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/* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
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/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
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/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
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/* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
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/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
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/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
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/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
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/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61"),
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/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65"),
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/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67"),
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/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73"),
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/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77"),
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/* 22 */ DECLARE_AMD_DEV("AMD5536"),
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};
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static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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amd_chipset = amd74xx_chipsets + id->driver_data;
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amd_config = amd_ide_chips + id->driver_data;
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if (dev->device != amd_config->id) {
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printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
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pci_name(dev), dev->device, amd_config->id);
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return -ENODEV;
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}
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return ide_setup_pci_device(dev, amd_chipset);
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}
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static const struct pci_device_id amd74xx_pci_tbl[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 },
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#ifdef CONFIG_BLK_DEV_IDE_SATA
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 },
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#endif
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 },
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#ifdef CONFIG_BLK_DEV_IDE_SATA
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 },
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#endif
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
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static struct pci_driver driver = {
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.name = "AMD_IDE",
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.id_table = amd74xx_pci_tbl,
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.probe = amd74xx_probe,
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};
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static int __init amd74xx_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(amd74xx_ide_init);
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MODULE_AUTHOR("Vojtech Pavlik");
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MODULE_DESCRIPTION("AMD PCI IDE driver");
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MODULE_LICENSE("GPL");
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