e86fe9f64d
This patch adds nic config handler for 5000 HW Family Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
520 lines
15 KiB
C
520 lines
15 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/wireless.h>
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#include <net/mac80211.h>
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#include <linux/etherdevice.h>
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#include <asm/unaligned.h>
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#include "iwl-eeprom.h"
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#include "iwl-4965.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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#include "iwl-5000-hw.h"
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#define IWL5000_UCODE_API "-1"
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static int iwl5000_apm_init(struct iwl_priv *priv)
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{
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int ret = 0;
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iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
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CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
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/* set "initialization complete" bit to move adapter
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* D0U* --> D0A* state */
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iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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/* wait for clock stabilization */
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ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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if (ret < 0) {
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IWL_DEBUG_INFO("Failed to init the card\n");
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return ret;
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}
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ret = iwl_grab_nic_access(priv);
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if (ret)
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return ret;
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/* enable DMA */
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iwl_write_prph(priv, APMG_CLK_EN_REG,
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APMG_CLK_VAL_DMA_CLK_RQT);
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udelay(20);
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iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
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APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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iwl_release_nic_access(priv);
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return ret;
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}
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static void iwl5000_nic_init(struct iwl_priv *priv)
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{
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unsigned long flags;
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u16 radio_cfg;
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u8 val_link;
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spin_lock_irqsave(&priv->lock, flags);
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pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
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/* disable L1 entry -- workaround for pre-B1 */
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pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
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radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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/* write radio config values to register */
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if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
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EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
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EEPROM_RF_CFG_DASH_MSK(radio_cfg));
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/* set CSR_HW_CONFIG_REG for uCode use */
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iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
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CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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/*
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* EEPROM
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*/
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static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
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{
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u16 offset = 0;
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if ((address & INDIRECT_ADDRESS) == 0)
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return address;
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switch (address & INDIRECT_TYPE_MSK) {
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case INDIRECT_HOST:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
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break;
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case INDIRECT_GENERAL:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
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break;
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case INDIRECT_REGULATORY:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
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break;
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case INDIRECT_CALIBRATION:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
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break;
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case INDIRECT_PROCESS_ADJST:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
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break;
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case INDIRECT_OTHERS:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
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break;
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default:
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IWL_ERROR("illegal indirect type: 0x%X\n",
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address & INDIRECT_TYPE_MSK);
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break;
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}
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/* translate the offset from words to byte */
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return (address & ADDRESS_MSK) + (offset << 1);
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}
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static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
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{
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u16 eeprom_ver;
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struct iwl_eeprom_calib_hdr {
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u8 version;
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u8 pa_type;
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u16 voltage;
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} *hdr;
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eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
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hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
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EEPROM_5000_CALIB_ALL);
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if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
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hdr->version < EEPROM_5000_TX_POWER_VERSION)
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goto err;
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return 0;
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err:
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IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
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eeprom_ver, EEPROM_5000_EEPROM_VERSION,
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hdr->version, EEPROM_5000_TX_POWER_VERSION);
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return -EINVAL;
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}
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#ifdef CONFIG_IWL5000_RUN_TIME_CALIB
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static void iwl5000_gain_computation(struct iwl_priv *priv,
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u32 average_noise[NUM_RX_CHAINS],
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u16 min_average_noise_antenna_i,
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u32 min_average_noise)
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{
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int i;
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s32 delta_g;
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struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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/* Find Gain Code for the antennas B and C */
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for (i = 1; i < NUM_RX_CHAINS; i++) {
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if ((data->disconn_array[i])) {
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data->delta_gain_code[i] = 0;
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continue;
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}
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delta_g = (1000 * ((s32)average_noise[0] -
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(s32)average_noise[i])) / 1500;
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/* bound gain by 2 bits value max, 3rd bit is sign */
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data->delta_gain_code[i] =
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min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
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if (delta_g < 0)
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/* set negative sign */
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data->delta_gain_code[i] |= (1 << 2);
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}
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IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
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data->delta_gain_code[1], data->delta_gain_code[2]);
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if (!data->radio_write) {
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struct iwl5000_calibration_chain_noise_gain_cmd cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
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cmd.delta_gain_1 = data->delta_gain_code[1];
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cmd.delta_gain_2 = data->delta_gain_code[2];
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iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
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sizeof(cmd), &cmd, NULL);
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data->radio_write = 1;
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data->state = IWL_CHAIN_NOISE_CALIBRATED;
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}
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data->chain_noise_a = 0;
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data->chain_noise_b = 0;
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data->chain_noise_c = 0;
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data->chain_signal_a = 0;
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data->chain_signal_b = 0;
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data->chain_signal_c = 0;
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data->beacon_count = 0;
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}
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static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
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{
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struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
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struct iwl5000_calibration_chain_noise_reset_cmd cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
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if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
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sizeof(cmd), &cmd))
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IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
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data->state = IWL_CHAIN_NOISE_ACCUMULATE;
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IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
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}
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}
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static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
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.min_nrg_cck = 95,
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.max_nrg_cck = 0,
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.auto_corr_min_ofdm = 90,
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.auto_corr_min_ofdm_mrc = 170,
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.auto_corr_min_ofdm_x1 = 120,
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.auto_corr_min_ofdm_mrc_x1 = 240,
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.auto_corr_max_ofdm = 120,
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.auto_corr_max_ofdm_mrc = 210,
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.auto_corr_max_ofdm_x1 = 155,
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.auto_corr_max_ofdm_mrc_x1 = 290,
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.auto_corr_min_cck = 125,
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.auto_corr_max_cck = 200,
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.auto_corr_min_cck_mrc = 170,
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.auto_corr_max_cck_mrc = 400,
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.nrg_th_cck = 95,
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.nrg_th_ofdm = 95,
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};
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#endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
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static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
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size_t offset)
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{
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u32 address = eeprom_indirect_address(priv, offset);
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BUG_ON(address >= priv->cfg->eeprom_size);
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return &priv->eeprom[address];
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}
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static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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{
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if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
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(priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
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IWL_ERROR("invalid queues_num, should be between %d and %d\n",
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IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
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return -EINVAL;
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}
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priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
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priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
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priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
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priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
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priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
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if (priv->cfg->mod_params->amsdu_size_8K)
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priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
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else
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priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
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priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
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priv->hw_params.max_stations = IWL5000_STATION_COUNT;
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priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
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priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
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priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
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priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
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priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
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BIT(IEEE80211_BAND_5GHZ);
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#ifdef CONFIG_IWL5000_RUN_TIME_CALIB
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priv->hw_params.sens = &iwl5000_sensitivity;
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#endif
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switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
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case CSR_HW_REV_TYPE_5100:
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case CSR_HW_REV_TYPE_5150:
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priv->hw_params.tx_chains_num = 1;
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priv->hw_params.rx_chains_num = 2;
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/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
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priv->hw_params.valid_tx_ant = ANT_A;
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priv->hw_params.valid_rx_ant = ANT_AB;
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break;
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case CSR_HW_REV_TYPE_5300:
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case CSR_HW_REV_TYPE_5350:
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priv->hw_params.tx_chains_num = 3;
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priv->hw_params.rx_chains_num = 3;
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priv->hw_params.valid_tx_ant = ANT_ABC;
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priv->hw_params.valid_rx_ant = ANT_ABC;
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break;
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}
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switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
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case CSR_HW_REV_TYPE_5100:
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case CSR_HW_REV_TYPE_5300:
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/* 5X00 wants in Celsius */
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priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
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break;
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case CSR_HW_REV_TYPE_5150:
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case CSR_HW_REV_TYPE_5350:
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/* 5X50 wants in Kelvin */
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priv->hw_params.ct_kill_threshold =
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CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
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break;
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}
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return 0;
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}
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static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
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{
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priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
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sizeof(struct iwl5000_shared),
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&priv->shared_phys);
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if (!priv->shared_virt)
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return -ENOMEM;
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memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
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return 0;
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}
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static void iwl5000_free_shared_mem(struct iwl_priv *priv)
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{
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if (priv->shared_virt)
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pci_free_consistent(priv->pci_dev,
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sizeof(struct iwl5000_shared),
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priv->shared_virt,
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priv->shared_phys);
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}
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/**
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* iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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*/
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static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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struct iwl4965_tx_queue *txq,
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u16 byte_cnt)
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{
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struct iwl5000_shared *shared_data = priv->shared_virt;
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int txq_id = txq->q.id;
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u8 sec_ctl = 0;
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u8 sta = 0;
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int len;
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len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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if (txq_id != IWL_CMD_QUEUE_NUM) {
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sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
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sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
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switch (sec_ctl & TX_CMD_SEC_MSK) {
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case TX_CMD_SEC_CCM:
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len += CCMP_MIC_LEN;
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break;
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case TX_CMD_SEC_TKIP:
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len += TKIP_ICV_LEN;
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break;
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case TX_CMD_SEC_WEP:
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len += WEP_IV_LEN + WEP_ICV_LEN;
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break;
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}
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}
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[txq->q.write_ptr], byte_cnt, len);
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[txq->q.write_ptr], sta_id, sta);
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if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
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byte_cnt, len);
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IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
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tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
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sta_id, sta);
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}
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}
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static struct iwl_hcmd_ops iwl5000_hcmd = {
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};
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static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
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#ifdef CONFIG_IWL5000_RUN_TIME_CALIB
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.gain_computation = iwl5000_gain_computation,
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.chain_noise_reset = iwl5000_chain_noise_reset,
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#endif
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};
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static struct iwl_lib_ops iwl5000_lib = {
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.set_hw_params = iwl5000_hw_set_hw_params,
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.alloc_shared_mem = iwl5000_alloc_shared_mem,
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.free_shared_mem = iwl5000_free_shared_mem,
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.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
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.apm_ops = {
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.init = iwl5000_apm_init,
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.config = iwl5000_nic_init,
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.set_pwr_src = iwl4965_set_pwr_src,
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},
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.eeprom_ops = {
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.regulatory_bands = {
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EEPROM_5000_REG_BAND_1_CHANNELS,
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EEPROM_5000_REG_BAND_2_CHANNELS,
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EEPROM_5000_REG_BAND_3_CHANNELS,
|
|
EEPROM_5000_REG_BAND_4_CHANNELS,
|
|
EEPROM_5000_REG_BAND_5_CHANNELS,
|
|
EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
|
|
EEPROM_5000_REG_BAND_52_FAT_CHANNELS
|
|
},
|
|
.verify_signature = iwlcore_eeprom_verify_signature,
|
|
.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
|
|
.release_semaphore = iwlcore_eeprom_release_semaphore,
|
|
.check_version = iwl5000_eeprom_check_version,
|
|
.query_addr = iwl5000_eeprom_query_addr,
|
|
},
|
|
};
|
|
|
|
static struct iwl_ops iwl5000_ops = {
|
|
.lib = &iwl5000_lib,
|
|
.hcmd = &iwl5000_hcmd,
|
|
.utils = &iwl5000_hcmd_utils,
|
|
};
|
|
|
|
static struct iwl_mod_params iwl50_mod_params = {
|
|
.num_of_queues = IWL50_NUM_QUEUES,
|
|
.enable_qos = 1,
|
|
.amsdu_size_8K = 1,
|
|
/* the rest are 0 by default */
|
|
};
|
|
|
|
|
|
struct iwl_cfg iwl5300_agn_cfg = {
|
|
.name = "5300AGN",
|
|
.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
.ops = &iwl5000_ops,
|
|
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
.mod_params = &iwl50_mod_params,
|
|
};
|
|
|
|
struct iwl_cfg iwl5100_agn_cfg = {
|
|
.name = "5100AGN",
|
|
.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
.ops = &iwl5000_ops,
|
|
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
.mod_params = &iwl50_mod_params,
|
|
};
|
|
|
|
struct iwl_cfg iwl5350_agn_cfg = {
|
|
.name = "5350AGN",
|
|
.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
|
|
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
|
|
.ops = &iwl5000_ops,
|
|
.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
|
|
.mod_params = &iwl50_mod_params,
|
|
};
|
|
|
|
module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
|
|
MODULE_PARM_DESC(disable50,
|
|
"manually disable the 50XX radio (default 0 [radio on])");
|
|
module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
|
|
MODULE_PARM_DESC(swcrypto50,
|
|
"using software crypto engine (default 0 [hardware])\n");
|
|
module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
|
|
MODULE_PARM_DESC(debug50, "50XX debug output mask");
|
|
module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
|
|
MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
|
|
module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
|
|
MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
|
|
module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
|
|
MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
|
|
|
|
|