e8768eeb59
Add top register access function. Signed-off-by: Juuso Oikarinen <juuso.oikarinen@nokia.com> Reviewed-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
444 lines
11 KiB
C
444 lines
11 KiB
C
/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/crc7.h>
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#include <linux/spi/spi.h>
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#include "wl1271.h"
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#include "wl12xx_80211.h"
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#include "wl1271_spi.h"
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static int wl1271_translate_addr(struct wl1271 *wl, int addr)
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{
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/*
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* To translate, first check to which window of addresses the
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* particular address belongs. Then subtract the starting address
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* of that window from the address. Then, add offset of the
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* translated region.
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*
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* The translated regions occur next to each other in physical device
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* memory, so just add the sizes of the preceeding address regions to
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* get the offset to the new region.
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*
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* Currently, only the two first regions are addressed, and the
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* assumption is that all addresses will fall into either of those
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* two.
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*/
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if ((addr >= wl->part.reg.start) &&
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(addr < wl->part.reg.start + wl->part.reg.size))
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return addr - wl->part.reg.start + wl->part.mem.size;
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else
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return addr - wl->part.mem.start;
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}
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void wl1271_spi_reset(struct wl1271 *wl)
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{
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u8 *cmd;
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struct spi_transfer t;
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struct spi_message m;
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cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
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if (!cmd) {
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wl1271_error("could not allocate cmd for spi reset");
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return;
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}
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memset(&t, 0, sizeof(t));
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spi_message_init(&m);
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memset(cmd, 0xff, WSPI_INIT_CMD_LEN);
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t.tx_buf = cmd;
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t.len = WSPI_INIT_CMD_LEN;
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spi_message_add_tail(&t, &m);
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spi_sync(wl->spi, &m);
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wl1271_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
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}
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void wl1271_spi_init(struct wl1271 *wl)
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{
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u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
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struct spi_transfer t;
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struct spi_message m;
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cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
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if (!cmd) {
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wl1271_error("could not allocate cmd for spi init");
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return;
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}
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memset(crc, 0, sizeof(crc));
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memset(&t, 0, sizeof(t));
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spi_message_init(&m);
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/*
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* Set WSPI_INIT_COMMAND
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* the data is being send from the MSB to LSB
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*/
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cmd[2] = 0xff;
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cmd[3] = 0xff;
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cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
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cmd[0] = 0;
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cmd[7] = 0;
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cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
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cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
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if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
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cmd[5] |= WSPI_INIT_CMD_DIS_FIXEDBUSY;
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else
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cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
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cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
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| WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
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crc[0] = cmd[1];
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crc[1] = cmd[0];
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crc[2] = cmd[7];
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crc[3] = cmd[6];
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crc[4] = cmd[5];
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cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
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cmd[4] |= WSPI_INIT_CMD_END;
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t.tx_buf = cmd;
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t.len = WSPI_INIT_CMD_LEN;
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spi_message_add_tail(&t, &m);
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spi_sync(wl->spi, &m);
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wl1271_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
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}
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/* Set the SPI partitions to access the chip addresses
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*
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* To simplify driver code, a fixed (virtual) memory map is defined for
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* register and memory addresses. Because in the chipset, in different stages
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* of operation, those addresses will move around, an address translation
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* mechanism is required.
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*
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* There are four partitions (three memory and one register partition),
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* which are mapped to two different areas of the hardware memory.
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*
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* Virtual address
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* space
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*
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* | |
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* ...+----+--> mem.start
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* Physical address ... | |
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* space ... | | [PART_0]
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* ... | |
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* 00000000 <--+----+... ...+----+--> mem.start + mem.size
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* | | ... | |
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* |MEM | ... | |
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* | | ... | |
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* mem.size <--+----+... | | {unused area)
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* | | ... | |
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* |REG | ... | |
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* mem.size | | ... | |
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* + <--+----+... ...+----+--> reg.start
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* reg.size | | ... | |
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* |MEM2| ... | | [PART_1]
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* | | ... | |
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* ...+----+--> reg.start + reg.size
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* | |
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*
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*/
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int wl1271_set_partition(struct wl1271 *wl,
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struct wl1271_partition_set *p)
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{
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/* copy partition info */
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memcpy(&wl->part, p, sizeof(*p));
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wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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p->mem.start, p->mem.size);
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wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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p->reg.start, p->reg.size);
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wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
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p->mem2.start, p->mem2.size);
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wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
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p->mem3.start, p->mem3.size);
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/* write partition info to the chipset */
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wl1271_write32(wl, HW_PART0_START_ADDR, p->mem.start);
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wl1271_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
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wl1271_write32(wl, HW_PART1_START_ADDR, p->reg.start);
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wl1271_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
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wl1271_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
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wl1271_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
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wl1271_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
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return 0;
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}
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#define WL1271_BUSY_WORD_TIMEOUT 1000
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void wl1271_spi_read_busy(struct wl1271 *wl, void *buf, size_t len)
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{
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struct spi_transfer t[1];
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struct spi_message m;
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u32 *busy_buf;
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int num_busy_bytes = 0;
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wl1271_info("spi read BUSY!");
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/*
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* Look for the non-busy word in the read buffer, and if found,
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* read in the remaining data into the buffer.
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*/
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busy_buf = (u32 *)buf;
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for (; (u32)busy_buf < (u32)buf + len; busy_buf++) {
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num_busy_bytes += sizeof(u32);
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if (*busy_buf & 0x1) {
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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memmove(buf, busy_buf, len - num_busy_bytes);
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t[0].rx_buf = buf + (len - num_busy_bytes);
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t[0].len = num_busy_bytes;
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spi_message_add_tail(&t[0], &m);
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spi_sync(wl->spi, &m);
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return;
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}
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}
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/*
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* Read further busy words from SPI until a non-busy word is
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* encountered, then read the data itself into the buffer.
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*/
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wl1271_info("spi read BUSY-polling needed!");
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num_busy_bytes = WL1271_BUSY_WORD_TIMEOUT;
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busy_buf = wl->buffer_busyword;
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while (num_busy_bytes) {
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num_busy_bytes--;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].rx_buf = busy_buf;
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t[0].len = sizeof(u32);
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spi_message_add_tail(&t[0], &m);
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spi_sync(wl->spi, &m);
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if (*busy_buf & 0x1) {
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].rx_buf = buf;
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t[0].len = len;
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spi_message_add_tail(&t[0], &m);
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spi_sync(wl->spi, &m);
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return;
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}
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}
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/* The SPI bus is unresponsive, the read failed. */
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memset(buf, 0, len);
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wl1271_error("SPI read busy-word timeout!\n");
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}
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void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf,
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size_t len, bool fixed)
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{
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struct spi_transfer t[3];
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struct spi_message m;
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u32 *busy_buf;
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u32 *cmd;
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cmd = &wl->buffer_cmd;
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busy_buf = wl->buffer_busyword;
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*cmd = 0;
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*cmd |= WSPI_CMD_READ;
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*cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
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*cmd |= addr & WSPI_CMD_BYTE_ADDR;
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if (fixed)
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*cmd |= WSPI_CMD_FIXED;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = cmd;
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t[0].len = 4;
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spi_message_add_tail(&t[0], &m);
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/* Busy and non busy words read */
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t[1].rx_buf = busy_buf;
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t[1].len = WL1271_BUSY_WORD_LEN;
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spi_message_add_tail(&t[1], &m);
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t[2].rx_buf = buf;
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t[2].len = len;
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spi_message_add_tail(&t[2], &m);
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spi_sync(wl->spi, &m);
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/* Check busy words */
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if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1))
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wl1271_spi_read_busy(wl, buf, len);
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wl1271_dump(DEBUG_SPI, "spi_read cmd -> ", cmd, sizeof(*cmd));
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wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, len);
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}
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void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf,
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size_t len, bool fixed)
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{
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struct spi_transfer t[2];
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struct spi_message m;
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u32 *cmd;
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cmd = &wl->buffer_cmd;
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*cmd = 0;
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*cmd |= WSPI_CMD_WRITE;
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*cmd |= (len << WSPI_CMD_BYTE_LENGTH_OFFSET) & WSPI_CMD_BYTE_LENGTH;
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*cmd |= addr & WSPI_CMD_BYTE_ADDR;
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if (fixed)
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*cmd |= WSPI_CMD_FIXED;
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = cmd;
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t[0].len = sizeof(*cmd);
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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t[1].len = len;
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spi_message_add_tail(&t[1], &m);
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spi_sync(wl->spi, &m);
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wl1271_dump(DEBUG_SPI, "spi_write cmd -> ", cmd, sizeof(*cmd));
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wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, len);
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}
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void wl1271_spi_mem_read(struct wl1271 *wl, int addr, void *buf,
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size_t len)
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{
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int physical;
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physical = wl1271_translate_addr(wl, addr);
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wl1271_spi_read(wl, physical, buf, len, false);
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}
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void wl1271_spi_mem_write(struct wl1271 *wl, int addr, void *buf,
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size_t len)
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{
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int physical;
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physical = wl1271_translate_addr(wl, addr);
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wl1271_spi_write(wl, physical, buf, len, false);
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}
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void wl1271_spi_reg_read(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed)
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{
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int physical;
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physical = wl1271_translate_addr(wl, addr);
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wl1271_spi_read(wl, physical, buf, len, fixed);
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}
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void wl1271_spi_reg_write(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed)
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{
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int physical;
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physical = wl1271_translate_addr(wl, addr);
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wl1271_spi_write(wl, physical, buf, len, fixed);
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}
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u32 wl1271_mem_read32(struct wl1271 *wl, int addr)
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{
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return wl1271_read32(wl, wl1271_translate_addr(wl, addr));
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}
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void wl1271_mem_write32(struct wl1271 *wl, int addr, u32 val)
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{
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wl1271_write32(wl, wl1271_translate_addr(wl, addr), val);
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}
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u32 wl1271_reg_read32(struct wl1271 *wl, int addr)
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{
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return wl1271_read32(wl, wl1271_translate_addr(wl, addr));
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}
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void wl1271_reg_write32(struct wl1271 *wl, int addr, u32 val)
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{
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wl1271_write32(wl, wl1271_translate_addr(wl, addr), val);
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}
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void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
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{
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/* write address >> 1 + 0x30000 to OCP_POR_CTR */
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addr = (addr >> 1) + 0x30000;
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wl1271_reg_write32(wl, OCP_POR_CTR, addr);
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/* write value to OCP_POR_WDATA */
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wl1271_reg_write32(wl, OCP_DATA_WRITE, val);
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/* write 1 to OCP_CMD */
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wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_WRITE);
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}
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u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
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{
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u32 val;
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int timeout = OCP_CMD_LOOP;
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/* write address >> 1 + 0x30000 to OCP_POR_CTR */
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addr = (addr >> 1) + 0x30000;
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wl1271_reg_write32(wl, OCP_POR_CTR, addr);
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/* write 2 to OCP_CMD */
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wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_READ);
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/* poll for data ready */
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do {
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val = wl1271_reg_read32(wl, OCP_DATA_READ);
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timeout--;
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} while (!(val & OCP_READY_MASK) && timeout);
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if (!timeout) {
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wl1271_warning("Top register access timed out.");
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return 0xffff;
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}
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/* check data status and return if OK */
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if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
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return val & 0xffff;
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else {
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wl1271_warning("Top register access returned error.");
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return 0xffff;
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}
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}
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