8678c1f042
Close a hole in the ASID version switch, particularly the following scenario: CPU0 MM PID CPU1 MM PID idle A pid(A) A idle(lazy tlb) * new asid version triggered by B * B pid(B) A pid(A) * MM A gets new asid version * A idle(lazy tlb) A pid(A) * CPU1 doesn't see the new ASID * The result is that CPU1 continues running with the hardware set for the original (stale) ASID value, but mm->context.id contains the new ASID value. The result is that the next MM fault on CPU1 updates the page table entries, but flush_tlb_page() fails due to wrong ASID. There is a related case with a threaded application is allocated a new ASID on one CPU while another of its threads is running on some different CPU. This scenario is not fixed by this commit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/*
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* linux/include/asm-arm/mmu_context.h
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*
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* Copyright (C) 1996 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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* 27-06-1996 RMK Created
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*/
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#ifndef __ASM_ARM_MMU_CONTEXT_H
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#define __ASM_ARM_MMU_CONTEXT_H
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#include <linux/compiler.h>
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#include <asm/cacheflush.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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void __check_kvm_seq(struct mm_struct *mm);
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#if __LINUX_ARM_ARCH__ >= 6
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/*
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* On ARMv6, we have the following structure in the Context ID:
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*
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* 31 7 0
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* +-------------------------+-----------+
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* | process ID | ASID |
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* +-------------------------+-----------+
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* | context ID |
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* +-------------------------------------+
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*
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* The ASID is used to tag entries in the CPU caches and TLBs.
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* The context ID is used by debuggers and trace logic, and
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* should be unique within all running processes.
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*/
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#define ASID_BITS 8
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#define ASID_MASK ((~0) << ASID_BITS)
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#define ASID_FIRST_VERSION (1 << ASID_BITS)
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extern unsigned int cpu_last_asid;
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void __new_context(struct mm_struct *mm);
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static inline void check_context(struct mm_struct *mm)
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{
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if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
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__new_context(mm);
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if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
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__check_kvm_seq(mm);
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}
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#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
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#else
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static inline void check_context(struct mm_struct *mm)
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{
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if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
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__check_kvm_seq(mm);
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}
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#define init_new_context(tsk,mm) 0
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#endif
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#define destroy_context(mm) do { } while(0)
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/*
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* This is called when "tsk" is about to enter lazy TLB mode.
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*
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* mm: describes the currently active mm context
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* tsk: task which is entering lazy tlb
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* cpu: cpu number which is entering lazy tlb
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*
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* tsk->mm will be NULL
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*/
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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#ifdef CONFIG_MMU
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unsigned int cpu = smp_processor_id();
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if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
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check_context(next);
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cpu_switch_mm(next->pgd, next);
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if (cache_is_vivt())
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cpu_clear(cpu, prev->cpu_vm_mask);
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}
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#endif
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, NULL)
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#endif
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