ed36959621
Add support for the VIA IDE controller that exists on the MPC8555 CDS system. Updated the config for the system to enable support by default. Signed-off-by: Scott Hall <shall@mvista.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
369 lines
9.8 KiB
C
369 lines
9.8 KiB
C
/*
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* arch/ppc/syslib/ppc85xx_setup.c
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*
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* MPC85XX common board code
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2004 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/serial.h>
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#include <linux/tty.h> /* for linux/serial_core.h */
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <asm/prom.h>
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#include <asm/time.h>
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#include <asm/mpc85xx.h>
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#include <asm/immap_85xx.h>
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#include <asm/mmu.h>
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#include <asm/ppc_sys.h>
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#include <asm/kgdb.h>
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#include <syslib/ppc85xx_setup.h>
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/* Return the amount of memory */
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unsigned long __init
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mpc85xx_find_end_of_memory(void)
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{
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bd_t *binfo;
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binfo = (bd_t *) __res;
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return binfo->bi_memsize;
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}
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/* The decrementer counts at the system (internal) clock freq divided by 8 */
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void __init
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mpc85xx_calibrate_decr(void)
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{
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bd_t *binfo = (bd_t *) __res;
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unsigned int freq, divisor;
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/* get the core frequency */
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freq = binfo->bi_busfreq;
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/* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
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divisor = 8;
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tb_ticks_per_jiffy = freq / divisor / HZ;
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tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
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/* Set the time base to zero */
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mtspr(SPRN_TBWL, 0);
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mtspr(SPRN_TBWU, 0);
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/* Clear any pending timer interrupts */
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mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
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/* Enable decrementer interrupt */
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mtspr(SPRN_TCR, TCR_DIE);
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}
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#ifdef CONFIG_SERIAL_8250
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void __init
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mpc85xx_early_serial_map(void)
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{
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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struct uart_port serial_req;
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#endif
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struct plat_serial8250_port *pdata;
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bd_t *binfo = (bd_t *) __res;
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pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
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/* Setup serial port access */
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pdata[0].uartclk = binfo->bi_busfreq;
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pdata[0].mapbase += binfo->bi_immr_base;
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pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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memset(&serial_req, 0, sizeof (serial_req));
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serial_req.iotype = SERIAL_IO_MEM;
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serial_req.mapbase = pdata[0].mapbase;
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serial_req.membase = pdata[0].membase;
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serial_req.regshift = 0;
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gen550_init(0, &serial_req);
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#endif
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pdata[1].uartclk = binfo->bi_busfreq;
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pdata[1].mapbase += binfo->bi_immr_base;
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pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Assume gen550_init() doesn't modify serial_req */
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serial_req.mapbase = pdata[1].mapbase;
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serial_req.membase = pdata[1].membase;
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gen550_init(1, &serial_req);
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#endif
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}
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#endif
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void
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mpc85xx_restart(char *cmd)
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{
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local_irq_disable();
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abort();
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}
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void
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mpc85xx_power_off(void)
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{
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local_irq_disable();
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for(;;);
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}
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void
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mpc85xx_halt(void)
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{
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local_irq_disable();
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for(;;);
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}
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#ifdef CONFIG_PCI
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#if defined(CONFIG_MPC8555_CDS)
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extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
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extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
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#endif
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static void __init
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mpc85xx_setup_pci1(struct pci_controller *hose)
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{
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volatile struct ccsr_pci *pci;
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volatile struct ccsr_guts *guts;
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unsigned short temps;
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bd_t *binfo = (bd_t *) __res;
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pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
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MPC85xx_PCI1_SIZE);
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guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
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MPC85xx_GUTS_SIZE);
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
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temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
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#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
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if (guts->pordevsr & PORDEVSR_PCI) {
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
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} else {
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/* PCI-X init */
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temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
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}
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/* Disable all windows (except powar0 since its ignored) */
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pci->powar1 = 0;
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pci->powar2 = 0;
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pci->powar3 = 0;
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pci->powar4 = 0;
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pci->piwar1 = 0;
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pci->piwar2 = 0;
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pci->piwar3 = 0;
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/* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
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pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
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pci->potear1 = 0x00000000;
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pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
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/* Enable, Mem R/W */
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pci->powar1 = 0x80044000 |
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(__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
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/* Setup outboud IO windows @ MPC85XX_PCI1_IO_BASE */
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pci->potar2 = 0x00000000;
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pci->potear2 = 0x00000000;
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pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
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/* Enable, IO R/W */
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pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
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/* Setup 2G inbound Memory Window @ 0 */
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pci->pitar1 = 0x00000000;
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pci->piwbar1 = 0x00000000;
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pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
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Mem, Snoop R/W, 2G */
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}
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extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
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extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
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#ifdef CONFIG_85xx_PCI2
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static void __init
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mpc85xx_setup_pci2(struct pci_controller *hose)
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{
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volatile struct ccsr_pci *pci;
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unsigned short temps;
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bd_t *binfo = (bd_t *) __res;
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pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
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MPC85xx_PCI2_SIZE);
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early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
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temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
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early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
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/* Disable all windows (except powar0 since its ignored) */
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pci->powar1 = 0;
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pci->powar2 = 0;
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pci->powar3 = 0;
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pci->powar4 = 0;
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pci->piwar1 = 0;
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pci->piwar2 = 0;
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pci->piwar3 = 0;
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/* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
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pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
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pci->potear1 = 0x00000000;
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pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
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/* Enable, Mem R/W */
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pci->powar1 = 0x80044000 |
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(__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
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/* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */
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pci->potar2 = 0x00000000;
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pci->potear2 = 0x00000000;
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pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
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/* Enable, IO R/W */
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pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
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/* Setup 2G inbound Memory Window @ 0 */
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pci->pitar1 = 0x00000000;
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pci->piwbar1 = 0x00000000;
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pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
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Mem, Snoop R/W, 2G */
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}
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#endif /* CONFIG_85xx_PCI2 */
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int mpc85xx_pci1_last_busno = 0;
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void __init
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mpc85xx_setup_hose(void)
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{
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struct pci_controller *hose_a;
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#ifdef CONFIG_85xx_PCI2
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struct pci_controller *hose_b;
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#endif
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bd_t *binfo = (bd_t *) __res;
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hose_a = pcibios_alloc_controller();
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if (!hose_a)
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return;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mpc85xx_map_irq;
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hose_a->first_busno = 0;
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hose_a->bus_offset = 0;
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hose_a->last_busno = 0xff;
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setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
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binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
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hose_a->set_cfg_type = 1;
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mpc85xx_setup_pci1(hose_a);
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hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
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hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
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hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
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hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
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hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
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hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
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#ifdef CONFIG_85xx_PCI2
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hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
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MPC85XX_PCI1_IO_SIZE +
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MPC85XX_PCI2_IO_SIZE);
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#else
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hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
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MPC85XX_PCI1_IO_SIZE);
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#endif
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isa_io_base = (unsigned long)hose_a->io_base_virt;
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/* setup resources */
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pci_init_resource(&hose_a->mem_resources[0],
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MPC85XX_PCI1_LOWER_MEM,
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MPC85XX_PCI1_UPPER_MEM,
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IORESOURCE_MEM, "PCI1 host bridge");
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pci_init_resource(&hose_a->io_resource,
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MPC85XX_PCI1_LOWER_IO,
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MPC85XX_PCI1_UPPER_IO,
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IORESOURCE_IO, "PCI1 host bridge");
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#if defined(CONFIG_MPC8555_CDS)
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/* Pre pciauto_bus_scan VIA init */
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mpc85xx_cds_enable_via(hose_a);
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#endif
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hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
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#if defined(CONFIG_MPC8555_CDS)
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/* Post pciauto_bus_scan VIA fixup */
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mpc85xx_cds_fixup_via(hose_a);
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#endif
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#ifdef CONFIG_85xx_PCI2
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hose_b = pcibios_alloc_controller();
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if (!hose_b)
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return;
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hose_b->bus_offset = hose_a->last_busno + 1;
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hose_b->first_busno = hose_a->last_busno + 1;
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hose_b->last_busno = 0xff;
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setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
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binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
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hose_b->set_cfg_type = 1;
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mpc85xx_setup_pci2(hose_b);
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hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
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hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
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hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
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hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
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hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
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hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
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hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
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/* setup resources */
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pci_init_resource(&hose_b->mem_resources[0],
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MPC85XX_PCI2_LOWER_MEM,
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MPC85XX_PCI2_UPPER_MEM,
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IORESOURCE_MEM, "PCI2 host bridge");
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pci_init_resource(&hose_b->io_resource,
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MPC85XX_PCI2_LOWER_IO,
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MPC85XX_PCI2_UPPER_IO,
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IORESOURCE_IO, "PCI2 host bridge");
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hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
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/* let board code know what the last bus number was on PCI1 */
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mpc85xx_pci1_last_busno = hose_a->last_busno;
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#endif
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return;
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}
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#endif /* CONFIG_PCI */
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