5e5e43c136
Porting the FDE functionality from msm-4.14 branch commit <b8f1b6a6> (Add support for block disk encryption). Modified to be compatible with the 5.4 Kernel. Test: 1. Basic_SimpleEncryption. 2. ModifyEnforcedFiles_FileCreationWithinEnforcedFolder. 3. PIN, pattern, password. 4. Verified filename encryption. 5. Generate/set ICE keys. 6. Enable ICE state for userdata partition. 7. Format the userdata partition. 8. Check if partition is encrypted via ICE. Change-Id: I307d75b7cdf25f7a9ad2b4f948e64d13278e6f03 Signed-off-by: Neeraj Soni <neersoni@codeaurora.org> Signed-off-by: Victor Zaharchuk <vzaharch@codeaurora.org>
164 lines
5.9 KiB
C
164 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_
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#define _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_
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#include <linux/io.h>
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/* Register bits for ICE version */
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#define ICE_CORE_CURRENT_MAJOR_VERSION 0x03
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#define ICE_CORE_STEP_REV_MASK 0xFFFF
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#define ICE_CORE_STEP_REV 0 /* bit 15-0 */
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#define ICE_CORE_MAJOR_REV_MASK 0xFF000000
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#define ICE_CORE_MAJOR_REV 24 /* bit 31-24 */
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#define ICE_CORE_MINOR_REV_MASK 0xFF0000
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#define ICE_CORE_MINOR_REV 16 /* bit 23-16 */
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#define ICE_BIST_STATUS_MASK (0xF0000000) /* bits 28-31 */
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#define ICE_FUSE_SETTING_MASK 0x1
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#define ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
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#define ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
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/* QTI ICE Registers from SWI */
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#define ICE_REGS_CONTROL 0x0000
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#define ICE_REGS_RESET 0x0004
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#define ICE_REGS_VERSION 0x0008
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#define ICE_REGS_FUSE_SETTING 0x0010
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#define ICE_REGS_PARAMETERS_1 0x0014
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#define ICE_REGS_PARAMETERS_2 0x0018
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#define ICE_REGS_PARAMETERS_3 0x001C
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#define ICE_REGS_PARAMETERS_4 0x0020
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#define ICE_REGS_PARAMETERS_5 0x0024
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/* QTI ICE v3.X only */
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#define ICE_GENERAL_ERR_STTS 0x0040
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#define ICE_INVALID_CCFG_ERR_STTS 0x0030
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#define ICE_GENERAL_ERR_MASK 0x0044
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/* QTI ICE v2.X only */
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#define ICE_REGS_NON_SEC_IRQ_STTS 0x0040
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#define ICE_REGS_NON_SEC_IRQ_MASK 0x0044
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#define ICE_REGS_NON_SEC_IRQ_CLR 0x0048
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#define ICE_REGS_STREAM1_ERROR_SYNDROME1 0x0050
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#define ICE_REGS_STREAM1_ERROR_SYNDROME2 0x0054
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#define ICE_REGS_STREAM2_ERROR_SYNDROME1 0x0058
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#define ICE_REGS_STREAM2_ERROR_SYNDROME2 0x005C
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#define ICE_REGS_STREAM1_BIST_ERROR_VEC 0x0060
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#define ICE_REGS_STREAM2_BIST_ERROR_VEC 0x0064
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#define ICE_REGS_STREAM1_BIST_FINISH_VEC 0x0068
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#define ICE_REGS_STREAM2_BIST_FINISH_VEC 0x006C
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#define ICE_REGS_BIST_STATUS 0x0070
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#define ICE_REGS_BYPASS_STATUS 0x0074
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#define ICE_REGS_ADVANCED_CONTROL 0x1000
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#define ICE_REGS_ENDIAN_SWAP 0x1004
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#define ICE_REGS_TEST_BUS_CONTROL 0x1010
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#define ICE_REGS_TEST_BUS_REG 0x1014
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#define ICE_REGS_STREAM1_COUNTERS1 0x1100
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#define ICE_REGS_STREAM1_COUNTERS2 0x1104
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#define ICE_REGS_STREAM1_COUNTERS3 0x1108
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#define ICE_REGS_STREAM1_COUNTERS4 0x110C
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#define ICE_REGS_STREAM1_COUNTERS5_MSB 0x1110
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#define ICE_REGS_STREAM1_COUNTERS5_LSB 0x1114
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#define ICE_REGS_STREAM1_COUNTERS6_MSB 0x1118
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#define ICE_REGS_STREAM1_COUNTERS6_LSB 0x111C
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#define ICE_REGS_STREAM1_COUNTERS7_MSB 0x1120
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#define ICE_REGS_STREAM1_COUNTERS7_LSB 0x1124
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#define ICE_REGS_STREAM1_COUNTERS8_MSB 0x1128
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#define ICE_REGS_STREAM1_COUNTERS8_LSB 0x112C
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#define ICE_REGS_STREAM1_COUNTERS9_MSB 0x1130
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#define ICE_REGS_STREAM1_COUNTERS9_LSB 0x1134
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#define ICE_REGS_STREAM2_COUNTERS1 0x1200
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#define ICE_REGS_STREAM2_COUNTERS2 0x1204
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#define ICE_REGS_STREAM2_COUNTERS3 0x1208
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#define ICE_REGS_STREAM2_COUNTERS4 0x120C
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#define ICE_REGS_STREAM2_COUNTERS5_MSB 0x1210
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#define ICE_REGS_STREAM2_COUNTERS5_LSB 0x1214
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#define ICE_REGS_STREAM2_COUNTERS6_MSB 0x1218
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#define ICE_REGS_STREAM2_COUNTERS6_LSB 0x121C
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#define ICE_REGS_STREAM2_COUNTERS7_MSB 0x1220
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#define ICE_REGS_STREAM2_COUNTERS7_LSB 0x1224
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#define ICE_REGS_STREAM2_COUNTERS8_MSB 0x1228
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#define ICE_REGS_STREAM2_COUNTERS8_LSB 0x122C
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#define ICE_REGS_STREAM2_COUNTERS9_MSB 0x1230
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#define ICE_REGS_STREAM2_COUNTERS9_LSB 0x1234
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#define ICE_STREAM1_PREMATURE_LBA_CHANGE (1L << 0)
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#define ICE_STREAM2_PREMATURE_LBA_CHANGE (1L << 1)
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#define ICE_STREAM1_NOT_EXPECTED_LBO (1L << 2)
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#define ICE_STREAM2_NOT_EXPECTED_LBO (1L << 3)
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#define ICE_STREAM1_NOT_EXPECTED_DUN (1L << 4)
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#define ICE_STREAM2_NOT_EXPECTED_DUN (1L << 5)
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#define ICE_STREAM1_NOT_EXPECTED_DUS (1L << 6)
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#define ICE_STREAM2_NOT_EXPECTED_DUS (1L << 7)
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#define ICE_STREAM1_NOT_EXPECTED_DBO (1L << 8)
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#define ICE_STREAM2_NOT_EXPECTED_DBO (1L << 9)
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#define ICE_STREAM1_NOT_EXPECTED_ENC_SEL (1L << 10)
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#define ICE_STREAM2_NOT_EXPECTED_ENC_SEL (1L << 11)
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#define ICE_STREAM1_NOT_EXPECTED_CONF_IDX (1L << 12)
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#define ICE_STREAM2_NOT_EXPECTED_CONF_IDX (1L << 13)
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#define ICE_STREAM1_NOT_EXPECTED_NEW_TRNS (1L << 14)
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#define ICE_STREAM2_NOT_EXPECTED_NEW_TRNS (1L << 15)
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#define ICE_NON_SEC_IRQ_MASK \
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(ICE_STREAM1_PREMATURE_LBA_CHANGE |\
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ICE_STREAM2_PREMATURE_LBA_CHANGE |\
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ICE_STREAM1_NOT_EXPECTED_LBO |\
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ICE_STREAM2_NOT_EXPECTED_LBO |\
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ICE_STREAM1_NOT_EXPECTED_DUN |\
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ICE_STREAM2_NOT_EXPECTED_DUN |\
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ICE_STREAM2_NOT_EXPECTED_DUS |\
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ICE_STREAM1_NOT_EXPECTED_DBO |\
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ICE_STREAM2_NOT_EXPECTED_DBO |\
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ICE_STREAM1_NOT_EXPECTED_ENC_SEL |\
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ICE_STREAM2_NOT_EXPECTED_ENC_SEL |\
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ICE_STREAM1_NOT_EXPECTED_CONF_IDX |\
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ICE_STREAM1_NOT_EXPECTED_NEW_TRNS |\
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ICE_STREAM2_NOT_EXPECTED_NEW_TRNS)
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/* QTI ICE registers from secure side */
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#define ICE_TEST_BUS_REG_SECURE_INTR (1L << 28)
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#define ICE_TEST_BUS_REG_NON_SECURE_INTR (1L << 2)
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#define ICE_LUT_KEYS_CRYPTOCFG_R_16 0x4040
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#define ICE_LUT_KEYS_CRYPTOCFG_R_17 0x4044
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#define ICE_LUT_KEYS_CRYPTOCFG_OFFSET 0x80
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#define ICE_LUT_KEYS_ICE_SEC_IRQ_STTS 0x6200
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#define ICE_LUT_KEYS_ICE_SEC_IRQ_MASK 0x6204
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#define ICE_LUT_KEYS_ICE_SEC_IRQ_CLR 0x6208
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#define ICE_STREAM1_PARTIALLY_SET_KEY_USED (1L << 0)
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#define ICE_STREAM2_PARTIALLY_SET_KEY_USED (1L << 1)
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#define ICE_QTIC_DBG_OPEN_EVENT (1L << 30)
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#define ICE_KEYS_RAM_RESET_COMPLETED (1L << 31)
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#define ICE_SEC_IRQ_MASK \
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(ICE_STREAM1_PARTIALLY_SET_KEY_USED |\
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ICE_STREAM2_PARTIALLY_SET_KEY_USED |\
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ICE_QTIC_DBG_OPEN_EVENT | \
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ICE_KEYS_RAM_RESET_COMPLETED)
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#define ice_writel(ice_entry, val, reg) \
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writel_relaxed((val), (ice_entry)->icemmio_base + (reg))
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#define ice_readl(ice_entry, reg) \
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readl_relaxed((ice_entry)->icemmio_base + (reg))
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#if IS_ENABLED(CONFIG_QTI_CRYPTO_FDE)
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#define crypto_qti_ice_writel(ice, val, reg) \
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writel_relaxed((val), (ice)->mmio + (reg))
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#define crypto_qti_ice_readl(ice, reg) \
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readl_relaxed((ice)->mmio + (reg))
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#endif //CONFIG_QTI_CRYPTO_FDE
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#endif /* _CRYPTO_INLINE_CRYPTO_ENGINE_REGS_H_ */
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