709 lines
18 KiB
C
709 lines
18 KiB
C
/*
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* cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
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* M (part of the Centrino chipset).
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*
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* Despite the "SpeedStep" in the name, this is almost entirely unlike
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* traditional SpeedStep.
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*
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* Modelled on speedstep.c
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*
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* Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
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*
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* WARNING WARNING WARNING
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*
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* This driver manipulates the PERF_CTL MSR, which is only somewhat
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* documented. While it seems to work on my laptop, it has not been
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* tested anywhere else, and it may not work for you, do strange
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* things or simply crash.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/config.h>
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#include <linux/sched.h> /* current */
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#include <linux/delay.h>
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#include <linux/compiler.h>
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#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
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#include <linux/acpi.h>
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#include <acpi/processor.h>
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#endif
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#define PFX "speedstep-centrino: "
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#define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>"
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
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struct cpu_id
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{
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__u8 x86; /* CPU family */
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__u8 x86_model; /* model */
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__u8 x86_mask; /* stepping */
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};
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enum {
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CPU_BANIAS,
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CPU_DOTHAN_A1,
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CPU_DOTHAN_A2,
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CPU_DOTHAN_B0,
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CPU_MP4HT_D0,
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CPU_MP4HT_E0,
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};
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static const struct cpu_id cpu_ids[] = {
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[CPU_BANIAS] = { 6, 9, 5 },
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[CPU_DOTHAN_A1] = { 6, 13, 1 },
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[CPU_DOTHAN_A2] = { 6, 13, 2 },
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[CPU_DOTHAN_B0] = { 6, 13, 6 },
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[CPU_MP4HT_D0] = {15, 3, 4 },
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[CPU_MP4HT_E0] = {15, 4, 1 },
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};
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#define N_IDS ARRAY_SIZE(cpu_ids)
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struct cpu_model
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{
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const struct cpu_id *cpu_id;
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const char *model_name;
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unsigned max_freq; /* max clock in kHz */
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struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
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};
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
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/* Operating points for current CPU */
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static struct cpu_model *centrino_model[NR_CPUS];
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static const struct cpu_id *centrino_cpu[NR_CPUS];
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static struct cpufreq_driver centrino_driver;
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#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
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/* Computes the correct form for IA32_PERF_CTL MSR for a particular
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frequency/voltage operating point; frequency in MHz, volts in mV.
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This is stored as "index" in the structure. */
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#define OP(mhz, mv) \
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{ \
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.frequency = (mhz) * 1000, \
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.index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
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}
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/*
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* These voltage tables were derived from the Intel Pentium M
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* datasheet, document 25261202.pdf, Table 5. I have verified they
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* are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
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* M.
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*/
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/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
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static struct cpufreq_frequency_table banias_900[] =
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{
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OP(600, 844),
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OP(800, 988),
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OP(900, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
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static struct cpufreq_frequency_table banias_1000[] =
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{
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OP(600, 844),
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OP(800, 972),
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OP(900, 988),
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OP(1000, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
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static struct cpufreq_frequency_table banias_1100[] =
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{
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OP( 600, 956),
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OP( 800, 1020),
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OP( 900, 1100),
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OP(1000, 1164),
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OP(1100, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
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static struct cpufreq_frequency_table banias_1200[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP( 900, 1020),
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OP(1000, 1100),
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OP(1100, 1164),
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OP(1200, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.30GHz (Banias) */
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static struct cpufreq_frequency_table banias_1300[] =
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{
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OP( 600, 956),
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OP( 800, 1260),
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OP(1000, 1292),
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OP(1200, 1356),
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OP(1300, 1388),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.40GHz (Banias) */
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static struct cpufreq_frequency_table banias_1400[] =
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{
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OP( 600, 956),
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OP( 800, 1180),
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OP(1000, 1308),
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OP(1200, 1436),
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OP(1400, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.50GHz (Banias) */
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static struct cpufreq_frequency_table banias_1500[] =
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{
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OP( 600, 956),
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OP( 800, 1116),
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OP(1000, 1228),
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OP(1200, 1356),
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OP(1400, 1452),
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OP(1500, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.60GHz (Banias) */
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static struct cpufreq_frequency_table banias_1600[] =
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{
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OP( 600, 956),
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OP( 800, 1036),
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OP(1000, 1164),
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OP(1200, 1276),
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OP(1400, 1420),
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OP(1600, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.70GHz (Banias) */
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static struct cpufreq_frequency_table banias_1700[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP(1000, 1116),
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OP(1200, 1228),
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OP(1400, 1308),
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OP(1700, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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#undef OP
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#define _BANIAS(cpuid, max, name) \
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{ .cpu_id = cpuid, \
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.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
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.max_freq = (max)*1000, \
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.op_points = banias_##max, \
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}
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#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
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/* CPU models, their operating frequency range, and freq/voltage
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operating points */
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static struct cpu_model models[] =
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{
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_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
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BANIAS(1000),
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BANIAS(1100),
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BANIAS(1200),
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BANIAS(1300),
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BANIAS(1400),
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BANIAS(1500),
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BANIAS(1600),
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BANIAS(1700),
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/* NULL model_name is a wildcard */
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{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
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{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
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{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
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{ NULL, }
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};
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#undef _BANIAS
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#undef BANIAS
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static int centrino_cpu_init_table(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
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struct cpu_model *model;
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for(model = models; model->cpu_id != NULL; model++)
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if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
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(model->model_name == NULL ||
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strcmp(cpu->x86_model_id, model->model_name) == 0))
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break;
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if (model->cpu_id == NULL) {
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/* No match at all */
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dprintk(KERN_INFO PFX "no support for CPU model \"%s\": "
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"send /proc/cpuinfo to " MAINTAINER "\n",
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cpu->x86_model_id);
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return -ENOENT;
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}
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if (model->op_points == NULL) {
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/* Matched a non-match */
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dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n",
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cpu->x86_model_id);
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#ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
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dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
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#endif
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return -ENOENT;
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}
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centrino_model[policy->cpu] = model;
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dprintk("found \"%s\": max frequency: %dkHz\n",
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model->model_name, model->max_freq);
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return 0;
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}
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#else
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static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
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#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
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{
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if ((c->x86 == x->x86) &&
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(c->x86_model == x->x86_model) &&
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(c->x86_mask == x->x86_mask))
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return 1;
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return 0;
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}
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/* To be called only after centrino_model is initialized */
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static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
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{
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int i;
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/*
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* Extract clock in kHz from PERF_CTL value
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* for centrino, as some DSDTs are buggy.
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* Ideally, this can be done using the acpi_data structure.
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*/
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if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
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(centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
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(centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
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msr = (msr >> 8) & 0xff;
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return msr * 100000;
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}
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if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
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return 0;
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msr &= 0xffff;
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for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
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if (msr == centrino_model[cpu]->op_points[i].index)
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return centrino_model[cpu]->op_points[i].frequency;
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}
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if (failsafe)
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return centrino_model[cpu]->op_points[i-1].frequency;
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else
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return 0;
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}
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/* Return the current CPU frequency in kHz */
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static unsigned int get_cur_freq(unsigned int cpu)
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{
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unsigned l, h;
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unsigned clock_freq;
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cpumask_t saved_mask;
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saved_mask = current->cpus_allowed;
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set_cpus_allowed(current, cpumask_of_cpu(cpu));
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if (smp_processor_id() != cpu)
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return 0;
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rdmsr(MSR_IA32_PERF_STATUS, l, h);
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clock_freq = extract_clock(l, cpu, 0);
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if (unlikely(clock_freq == 0)) {
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/*
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* On some CPUs, we can see transient MSR values (which are
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* not present in _PSS), while CPU is doing some automatic
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* P-state transition (like TM2). Get the last freq set
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* in PERF_CTL.
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*/
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rdmsr(MSR_IA32_PERF_CTL, l, h);
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clock_freq = extract_clock(l, cpu, 1);
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}
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set_cpus_allowed(current, saved_mask);
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return clock_freq;
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}
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#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
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static struct acpi_processor_performance p;
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/*
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* centrino_cpu_init_acpi - register with ACPI P-States library
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*
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* Register with the ACPI P-States library (part of drivers/acpi/processor.c)
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* in order to determine correct frequency and voltage pairings by reading
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* the _PSS of the ACPI DSDT or SSDT tables.
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*/
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static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
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{
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unsigned long cur_freq;
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int result = 0, i;
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unsigned int cpu = policy->cpu;
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/* register with ACPI core */
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if (acpi_processor_register_performance(&p, cpu)) {
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dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
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return -EIO;
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}
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/* verify the acpi_data */
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if (p.state_count <= 1) {
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dprintk("No P-States\n");
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result = -ENODEV;
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goto err_unreg;
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}
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if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
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(p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
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dprintk("Invalid control/status registers (%x - %x)\n",
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p.control_register.space_id, p.status_register.space_id);
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result = -EIO;
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goto err_unreg;
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}
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for (i=0; i<p.state_count; i++) {
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if (p.states[i].control != p.states[i].status) {
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dprintk("Different control (%llu) and status values (%llu)\n",
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p.states[i].control, p.states[i].status);
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result = -EINVAL;
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goto err_unreg;
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}
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if (!p.states[i].core_frequency) {
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dprintk("Zero core frequency for state %u\n", i);
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result = -EINVAL;
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goto err_unreg;
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}
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if (p.states[i].core_frequency > p.states[0].core_frequency) {
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dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
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p.states[i].core_frequency, p.states[0].core_frequency);
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p.states[i].core_frequency = 0;
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continue;
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}
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}
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centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
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if (!centrino_model[cpu]) {
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result = -ENOMEM;
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goto err_unreg;
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}
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centrino_model[cpu]->model_name=NULL;
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centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000;
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centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
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(p.state_count + 1), GFP_KERNEL);
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if (!centrino_model[cpu]->op_points) {
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result = -ENOMEM;
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goto err_kfree;
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}
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for (i=0; i<p.state_count; i++) {
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centrino_model[cpu]->op_points[i].index = p.states[i].control;
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centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000;
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dprintk("adding state %i with frequency %u and control value %04x\n",
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i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
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}
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centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
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cur_freq = get_cur_freq(cpu);
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for (i=0; i<p.state_count; i++) {
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if (!p.states[i].core_frequency) {
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dprintk("skipping state %u\n", i);
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centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
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continue;
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}
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if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
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(centrino_model[cpu]->op_points[i].frequency)) {
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dprintk("Invalid encoded frequency (%u vs. %u)\n",
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extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
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centrino_model[cpu]->op_points[i].frequency);
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result = -EINVAL;
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goto err_kfree_all;
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}
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if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
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p.state = i;
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}
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/* notify BIOS that we exist */
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acpi_processor_notify_smm(THIS_MODULE);
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return 0;
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err_kfree_all:
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kfree(centrino_model[cpu]->op_points);
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err_kfree:
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kfree(centrino_model[cpu]);
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err_unreg:
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acpi_processor_unregister_performance(&p, cpu);
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dprintk(KERN_INFO PFX "invalid ACPI data\n");
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return (result);
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}
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#else
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static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
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#endif
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static int centrino_cpu_init(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
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unsigned freq;
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unsigned l, h;
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int ret;
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int i;
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struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
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/* Only Intel makes Enhanced Speedstep-capable CPUs */
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if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
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return -ENODEV;
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if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
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centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
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}
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if (centrino_cpu_init_acpi(policy)) {
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if (policy->cpu != 0)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < N_IDS; i++)
|
|
if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
|
|
break;
|
|
|
|
if (i != N_IDS)
|
|
centrino_cpu[policy->cpu] = &cpu_ids[i];
|
|
|
|
if (!centrino_cpu[policy->cpu]) {
|
|
dprintk(KERN_INFO PFX "found unsupported CPU with "
|
|
"Enhanced SpeedStep: send /proc/cpuinfo to "
|
|
MAINTAINER "\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (centrino_cpu_init_table(policy)) {
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
/* Check to see if Enhanced SpeedStep is enabled, and try to
|
|
enable it if not. */
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
if (!(l & (1<<16))) {
|
|
l |= (1<<16);
|
|
dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
|
|
wrmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
/* check to see if it stuck */
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
if (!(l & (1<<16))) {
|
|
printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
freq = get_cur_freq(policy->cpu);
|
|
|
|
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
|
|
policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
|
|
policy->cur = freq;
|
|
|
|
dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
|
|
|
|
ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
|
|
if (ret)
|
|
return (ret);
|
|
|
|
cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int centrino_cpu_exit(struct cpufreq_policy *policy)
|
|
{
|
|
unsigned int cpu = policy->cpu;
|
|
|
|
if (!centrino_model[cpu])
|
|
return -ENODEV;
|
|
|
|
cpufreq_frequency_table_put_attr(cpu);
|
|
|
|
#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
|
|
if (!centrino_model[cpu]->model_name) {
|
|
dprintk("unregistering and freeing ACPI data\n");
|
|
acpi_processor_unregister_performance(&p, cpu);
|
|
kfree(centrino_model[cpu]->op_points);
|
|
kfree(centrino_model[cpu]);
|
|
}
|
|
#endif
|
|
|
|
centrino_model[cpu] = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* centrino_verify - verifies a new CPUFreq policy
|
|
* @policy: new policy
|
|
*
|
|
* Limit must be within this model's frequency range at least one
|
|
* border included.
|
|
*/
|
|
static int centrino_verify (struct cpufreq_policy *policy)
|
|
{
|
|
return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
|
|
}
|
|
|
|
/**
|
|
* centrino_setpolicy - set a new CPUFreq policy
|
|
* @policy: new policy
|
|
* @target_freq: the target frequency
|
|
* @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
|
|
*
|
|
* Sets a new CPUFreq policy.
|
|
*/
|
|
static int centrino_target (struct cpufreq_policy *policy,
|
|
unsigned int target_freq,
|
|
unsigned int relation)
|
|
{
|
|
unsigned int newstate = 0;
|
|
unsigned int msr, oldmsr, h, cpu = policy->cpu;
|
|
struct cpufreq_freqs freqs;
|
|
cpumask_t saved_mask;
|
|
int retval;
|
|
|
|
if (centrino_model[cpu] == NULL)
|
|
return -ENODEV;
|
|
|
|
/*
|
|
* Support for SMP systems.
|
|
* Make sure we are running on the CPU that wants to change frequency
|
|
*/
|
|
saved_mask = current->cpus_allowed;
|
|
set_cpus_allowed(current, policy->cpus);
|
|
if (!cpu_isset(smp_processor_id(), policy->cpus)) {
|
|
dprintk("couldn't limit to CPUs in this domain\n");
|
|
return(-EAGAIN);
|
|
}
|
|
|
|
if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq,
|
|
relation, &newstate)) {
|
|
retval = -EINVAL;
|
|
goto migrate_end;
|
|
}
|
|
|
|
msr = centrino_model[cpu]->op_points[newstate].index;
|
|
rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
|
|
|
|
if (msr == (oldmsr & 0xffff)) {
|
|
retval = 0;
|
|
dprintk("no change needed - msr was and needs to be %x\n", oldmsr);
|
|
goto migrate_end;
|
|
}
|
|
|
|
freqs.cpu = cpu;
|
|
freqs.old = extract_clock(oldmsr, cpu, 0);
|
|
freqs.new = extract_clock(msr, cpu, 0);
|
|
|
|
dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
|
|
target_freq, freqs.old, freqs.new, msr);
|
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
|
|
|
/* all but 16 LSB are "reserved", so treat them with
|
|
care */
|
|
oldmsr &= ~0xffff;
|
|
msr &= 0xffff;
|
|
oldmsr |= msr;
|
|
|
|
wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
|
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
|
|
|
retval = 0;
|
|
migrate_end:
|
|
set_cpus_allowed(current, saved_mask);
|
|
return (retval);
|
|
}
|
|
|
|
static struct freq_attr* centrino_attr[] = {
|
|
&cpufreq_freq_attr_scaling_available_freqs,
|
|
NULL,
|
|
};
|
|
|
|
static struct cpufreq_driver centrino_driver = {
|
|
.name = "centrino", /* should be speedstep-centrino,
|
|
but there's a 16 char limit */
|
|
.init = centrino_cpu_init,
|
|
.exit = centrino_cpu_exit,
|
|
.verify = centrino_verify,
|
|
.target = centrino_target,
|
|
.get = get_cur_freq,
|
|
.attr = centrino_attr,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
|
|
/**
|
|
* centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
|
|
*
|
|
* Initializes the Enhanced SpeedStep support. Returns -ENODEV on
|
|
* unsupported devices, -ENOENT if there's no voltage table for this
|
|
* particular CPU model, -EINVAL on problems during initiatization,
|
|
* and zero on success.
|
|
*
|
|
* This is quite picky. Not only does the CPU have to advertise the
|
|
* "est" flag in the cpuid capability flags, we look for a specific
|
|
* CPU model and stepping, and we need to have the exact model name in
|
|
* our voltage tables. That is, be paranoid about not releasing
|
|
* someone's valuable magic smoke.
|
|
*/
|
|
static int __init centrino_init(void)
|
|
{
|
|
struct cpuinfo_x86 *cpu = cpu_data;
|
|
|
|
if (!cpu_has(cpu, X86_FEATURE_EST))
|
|
return -ENODEV;
|
|
|
|
return cpufreq_register_driver(¢rino_driver);
|
|
}
|
|
|
|
static void __exit centrino_exit(void)
|
|
{
|
|
cpufreq_unregister_driver(¢rino_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
|
|
MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
|
|
MODULE_LICENSE ("GPL");
|
|
|
|
late_initcall(centrino_init);
|
|
module_exit(centrino_exit);
|