1d89a7f072
now that it is the same between arches, put it into smpboot.c Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
393 lines
9.8 KiB
C
393 lines
9.8 KiB
C
#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/percpu.h>
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#include <linux/bootmem.h>
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#include <asm/nmi.h>
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#include <asm/irq.h>
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#include <asm/smp.h>
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#include <asm/cpu.h>
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#include <asm/numa.h>
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/* Number of siblings per CPU package */
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int smp_num_siblings = 1;
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EXPORT_SYMBOL(smp_num_siblings);
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/* Last level cache ID of each logical CPU */
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DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
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/* bitmap of online cpus */
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cpumask_t cpu_online_map __read_mostly;
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EXPORT_SYMBOL(cpu_online_map);
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cpumask_t cpu_callin_map;
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cpumask_t cpu_callout_map;
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cpumask_t cpu_possible_map;
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EXPORT_SYMBOL(cpu_possible_map);
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/* representing HT siblings of each logical CPU */
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DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
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EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
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/* representing HT and core siblings of each logical CPU */
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DEFINE_PER_CPU(cpumask_t, cpu_core_map);
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EXPORT_PER_CPU_SYMBOL(cpu_core_map);
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/* Per CPU bogomips and other parameters */
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DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
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EXPORT_PER_CPU_SYMBOL(cpu_info);
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/* ready for x86_64, no harm for x86, since it will overwrite after alloc */
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unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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#ifdef CONFIG_X86_32
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/* Set if we find a B stepping CPU */
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int __cpuinitdata smp_b_stepping;
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#endif
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static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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/*
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* Mask B, Pentium, but not Pentium MMX
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*/
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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c->x86 == 5 &&
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c->x86_mask >= 1 && c->x86_mask <= 4 &&
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c->x86_model <= 3)
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/*
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* Remember we have B step Pentia with bugs
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*/
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smp_b_stepping = 1;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
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if (num_possible_cpus() == 1)
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goto valid_k7;
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/* Athlon 660/661 is valid. */
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if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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(c->x86_mask == 1)))
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goto valid_k7;
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/* Duron 670 is valid */
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if ((c->x86_model == 7) && (c->x86_mask == 0))
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goto valid_k7;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability
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* bit. It's worth noting that the A5 stepping (662) of some
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* Athlon XP's have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has_mp)
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goto valid_k7;
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/* If we get here, not a certified SMP capable AMD system. */
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add_taint(TAINT_UNSAFE_SMP);
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}
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valid_k7:
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;
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#endif
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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*/
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void __cpuinit smp_store_cpu_info(int id)
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{
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struct cpuinfo_x86 *c = &cpu_data(id);
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*c = boot_cpu_data;
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c->cpu_index = id;
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if (id != 0)
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identify_secondary_cpu(c);
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smp_apply_quirks(c);
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}
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void __cpuinit set_cpu_sibling_map(int cpu)
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{
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int i;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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cpu_set(cpu, cpu_sibling_setup_map);
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if (smp_num_siblings > 1) {
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for_each_cpu_mask(i, cpu_sibling_setup_map) {
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if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
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c->cpu_core_id == cpu_data(i).cpu_core_id) {
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cpu_set(i, per_cpu(cpu_sibling_map, cpu));
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cpu_set(cpu, per_cpu(cpu_sibling_map, i));
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cpu_set(i, per_cpu(cpu_core_map, cpu));
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cpu_set(cpu, per_cpu(cpu_core_map, i));
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cpu_set(i, c->llc_shared_map);
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cpu_set(cpu, cpu_data(i).llc_shared_map);
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}
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}
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} else {
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cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
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}
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cpu_set(cpu, c->llc_shared_map);
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if (current_cpu_data.x86_max_cores == 1) {
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per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
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c->booted_cores = 1;
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return;
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}
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for_each_cpu_mask(i, cpu_sibling_setup_map) {
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if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
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per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
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cpu_set(i, c->llc_shared_map);
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cpu_set(cpu, cpu_data(i).llc_shared_map);
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}
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if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
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cpu_set(i, per_cpu(cpu_core_map, cpu));
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cpu_set(cpu, per_cpu(cpu_core_map, i));
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/*
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* Does this new cpu bringup a new core?
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*/
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if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
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/*
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* for each core in package, increment
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* the booted_cores for this new cpu
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*/
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if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
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c->booted_cores++;
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/*
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* increment the core count for all
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* the other cpus in this package
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*/
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if (i != cpu)
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cpu_data(i).booted_cores++;
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} else if (i != cpu && !c->booted_cores)
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c->booted_cores = cpu_data(i).booted_cores;
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}
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}
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}
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/* maps the cpu to the sched domain representing multi-core */
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cpumask_t cpu_coregroup_map(int cpu)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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/*
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* For perf, we return last level cache shared map.
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* And for power savings, we return cpu_core_map
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*/
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if (sched_mc_power_savings || sched_smt_power_savings)
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return per_cpu(cpu_core_map, cpu);
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else
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return c->llc_shared_map;
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}
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/*
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* Currently trivial. Write the real->protected mode
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* bootstrap into the page concerned. The caller
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* has made sure it's suitably aligned.
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*/
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unsigned long __cpuinit setup_trampoline(void)
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{
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memcpy(trampoline_base, trampoline_data,
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trampoline_end - trampoline_data);
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return virt_to_phys(trampoline_base);
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}
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#ifdef CONFIG_X86_32
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/*
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* We are called very early to get the low memory for the
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* SMP bootup trampoline page.
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*/
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void __init smp_alloc_memory(void)
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{
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trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
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/*
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* Has to be in very low memory so we can execute
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* real-mode AP code.
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*/
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if (__pa(trampoline_base) >= 0x9F000)
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BUG();
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}
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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void remove_siblinginfo(int cpu)
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{
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int sibling;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
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cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
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/*/
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* last thread sibling in this cpu core going down
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*/
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if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
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cpu_data(sibling).booted_cores--;
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}
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for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
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cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
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cpus_clear(per_cpu(cpu_sibling_map, cpu));
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cpus_clear(per_cpu(cpu_core_map, cpu));
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c->phys_proc_id = 0;
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c->cpu_core_id = 0;
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cpu_clear(cpu, cpu_sibling_setup_map);
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}
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int additional_cpus __initdata = -1;
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static __init int setup_additional_cpus(char *s)
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{
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return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
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}
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early_param("additional_cpus", setup_additional_cpus);
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/*
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* cpu_possible_map should be static, it cannot change as cpu's
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* are onlined, or offlined. The reason is per-cpu data-structures
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* are allocated by some modules at init time, and dont expect to
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* do this dynamically on cpu arrival/departure.
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* cpu_present_map on the other hand can change dynamically.
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* In case when cpu_hotplug is not compiled, then we resort to current
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* behaviour, which is cpu_possible == cpu_present.
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* - Ashok Raj
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*
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* Three ways to find out the number of additional hotplug CPUs:
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* - If the BIOS specified disabled CPUs in ACPI/mptables use that.
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* - The user can overwrite it with additional_cpus=NUM
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* - Otherwise don't reserve additional CPUs.
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* We do this because additional CPUs waste a lot of memory.
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* -AK
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*/
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__init void prefill_possible_map(void)
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{
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int i;
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int possible;
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if (additional_cpus == -1) {
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if (disabled_cpus > 0)
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additional_cpus = disabled_cpus;
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else
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additional_cpus = 0;
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}
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possible = num_processors + additional_cpus;
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if (possible > NR_CPUS)
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possible = NR_CPUS;
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printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
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possible, max_t(int, possible - num_processors, 0));
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for (i = 0; i < possible; i++)
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cpu_set(i, cpu_possible_map);
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}
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static void __ref remove_cpu_from_maps(int cpu)
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{
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cpu_clear(cpu, cpu_online_map);
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#ifdef CONFIG_X86_64
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cpu_clear(cpu, cpu_callout_map);
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cpu_clear(cpu, cpu_callin_map);
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/* was set by cpu_init() */
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clear_bit(cpu, (unsigned long *)&cpu_initialized);
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clear_node_cpumask(cpu);
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#endif
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}
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int __cpu_disable(void)
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{
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int cpu = smp_processor_id();
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/*
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* Perhaps use cpufreq to drop frequency, but that could go
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* into generic code.
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*
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* We won't take down the boot processor on i386 due to some
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* interrupts only being able to be serviced by the BSP.
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* Especially so if we're not using an IOAPIC -zwane
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*/
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if (cpu == 0)
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return -EBUSY;
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if (nmi_watchdog == NMI_LOCAL_APIC)
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stop_apic_nmi_watchdog(NULL);
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clear_local_APIC();
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/*
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* HACK:
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* Allow any queued timer interrupts to get serviced
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* This is only a temporary solution until we cleanup
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* fixup_irqs as we do for IA64.
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*/
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local_irq_enable();
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mdelay(1);
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local_irq_disable();
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remove_siblinginfo(cpu);
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/* It's now safe to remove this processor from the online map */
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remove_cpu_from_maps(cpu);
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fixup_irqs(cpu_online_map);
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return 0;
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}
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void __cpu_die(unsigned int cpu)
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{
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/* We don't do anything here: idle task is faking death itself. */
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unsigned int i;
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for (i = 0; i < 10; i++) {
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/* They ack this in play_dead by setting CPU_DEAD */
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if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
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printk(KERN_INFO "CPU %d is now offline\n", cpu);
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if (1 == num_online_cpus())
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alternatives_smp_switch(0);
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return;
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}
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msleep(100);
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}
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printk(KERN_ERR "CPU %u didn't die...\n", cpu);
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}
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#else /* ... !CONFIG_HOTPLUG_CPU */
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int __cpu_disable(void)
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{
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return -ENOSYS;
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}
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void __cpu_die(unsigned int cpu)
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{
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/* We said "no" in __cpu_disable */
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BUG();
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}
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#endif
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/*
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* If the BIOS enumerates physical processors before logical,
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* maxcpus=N at enumeration-time can be used to disable HT.
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*/
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static int __init parse_maxcpus(char *arg)
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{
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extern unsigned int maxcpus;
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maxcpus = simple_strtoul(arg, NULL, 0);
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return 0;
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}
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early_param("maxcpus", parse_maxcpus);
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