1394f03221
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
692 lines
29 KiB
C
692 lines
29 KiB
C
/*
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* File: include/asm-blackfin/mach-common/def_LPBlackfin.h
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* Based on:
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* Author: unknown
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* COPYRIGHT 2005 Analog Devices
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* Created: ?
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* Description:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
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#ifndef _DEF_LPBLACKFIN_H
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#define _DEF_LPBLACKFIN_H
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#include <asm/mach/anomaly.h>
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/*#if !defined(__ADSPLPBLACKFIN__)
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#warning def_LPBlackfin.h should only be included for 532 compatible chips.
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#endif
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*/
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#define MK_BMSK_(x) (1<<x)
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#if defined(ANOMALY_05000198)
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#define bfin_read16(addr) ({ unsigned __v; \
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__asm__ __volatile__ ("NOP;\n\t"\
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"%0 = w[%1] (z);\n\t"\
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: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
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#define bfin_read32(addr) ({ unsigned __v; \
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__asm__ __volatile__ ("NOP;\n\t"\
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"%0 = [%1];\n\t"\
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: "=d"(__v) : "a"(addr)); __v; })
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#define bfin_write16(addr,val) ({\
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__asm__ __volatile__ ("NOP;\n\t"\
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"w[%0] = %1;\n\t"\
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: : "a"(addr) , "d"(val) : "memory");})
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#define bfin_write32(addr,val) ({\
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__asm__ __volatile__ ("NOP;\n\t"\
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"[%0] = %1;\n\t"\
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: : "a"(addr) , "d"(val) : "memory");})
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#else
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#define bfin_read16(addr) ({ unsigned __v; \
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__asm__ __volatile__ (\
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"%0 = w[%1] (z);\n\t"\
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: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
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#define bfin_read32(addr) ({ unsigned __v; \
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__asm__ __volatile__ (\
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"%0 = [%1];\n\t"\
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: "=d"(__v) : "a"(addr)); __v; })
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#define bfin_write16(addr,val) ({\
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__asm__ __volatile__ (\
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"w[%0] = %1;\n\t"\
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: : "a"(addr) , "d"(val) : "memory");})
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#define bfin_write32(addr,val) ({\
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__asm__ __volatile__ (\
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"[%0] = %1;\n\t"\
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: : "a"(addr) , "d"(val) : "memory");})
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#endif
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/**************************************************
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* System Register Bits
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**************************************************/
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/**************************************************
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* ASTAT register
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**************************************************/
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/* definitions of ASTAT bit positions*/
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/*Result of last ALU0 or shifter operation is zero*/
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#define ASTAT_AZ_P 0x00000000
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/*Result of last ALU0 or shifter operation is negative*/
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#define ASTAT_AN_P 0x00000001
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/*Condition Code, used for holding comparison results*/
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#define ASTAT_CC_P 0x00000005
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/*Quotient Bit*/
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#define ASTAT_AQ_P 0x00000006
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/*Rounding mode, set for biased, clear for unbiased*/
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#define ASTAT_RND_MOD_P 0x00000008
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/*Result of last ALU0 operation generated a carry*/
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#define ASTAT_AC0_P 0x0000000C
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/*Result of last ALU0 operation generated a carry*/
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#define ASTAT_AC0_COPY_P 0x00000002
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/*Result of last ALU1 operation generated a carry*/
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#define ASTAT_AC1_P 0x0000000D
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/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
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#define ASTAT_AV0_P 0x00000010
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/*Sticky version of ASTAT_AV0 */
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#define ASTAT_AV0S_P 0x00000011
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/*Result of last MAC1 operation overflowed, sticky for MAC*/
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#define ASTAT_AV1_P 0x00000012
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/*Sticky version of ASTAT_AV1 */
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#define ASTAT_AV1S_P 0x00000013
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/*Result of last ALU0 or MAC0 operation overflowed*/
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#define ASTAT_V_P 0x00000018
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/*Result of last ALU0 or MAC0 operation overflowed*/
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#define ASTAT_V_COPY_P 0x00000003
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/*Sticky version of ASTAT_V*/
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#define ASTAT_VS_P 0x00000019
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/* Masks */
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/*Result of last ALU0 or shifter operation is zero*/
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#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
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/*Result of last ALU0 or shifter operation is negative*/
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#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
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/*Result of last ALU0 operation generated a carry*/
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#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
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/*Result of last ALU0 operation generated a carry*/
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#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
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/*Result of last ALU0 operation generated a carry*/
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#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
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/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
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#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
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/*Result of last MAC1 operation overflowed, sticky for MAC*/
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#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
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/*Condition Code, used for holding comparison results*/
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#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
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/*Quotient Bit*/
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#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
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/*Rounding mode, set for biased, clear for unbiased*/
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#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
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/*Overflow Bit*/
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#define ASTAT_V MK_BMSK_(ASTAT_V_P)
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/*Overflow Bit*/
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#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
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/**************************************************
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* SEQSTAT register
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**************************************************/
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/* Bit Positions */
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#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
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#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
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#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
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#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
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#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
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#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
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#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
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* set by IDLE instruction.
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*/
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#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
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* reset was a software reset
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* (=1)
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*/
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#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
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#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
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#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
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#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
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#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
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/* Masks */
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/* Exception cause */
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#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
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MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
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MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
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MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
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MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
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MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
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0)
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/* Indicates whether the last reset was a software reset (=1) */
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#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
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/* Last hw error cause */
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#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
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MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
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MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
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MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
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MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
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0)
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/* Translate bits to something useful */
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/* Last hw error cause */
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#define SEQSTAT_HWERRCAUSE_SHIFT (14)
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#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
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#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
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#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
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#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
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/**************************************************
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* SYSCFG register
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**************************************************/
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/* Bit Positions */
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#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
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* set it forces an exception
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* for each instruction executed
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*/
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#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
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#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
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/* Masks */
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/* Supervisor single step, when set it forces an exception for each
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*instruction executed
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*/
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#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
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/* Enable cycle counter (=1) */
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#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
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/* Self Nesting Interrupt Enable */
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#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
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/* Backward-compatibility for typos in prior releases */
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#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
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#define SYSCFG_CCCEN SYSCFG_CCEN
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/****************************************************
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* Core MMR Register Map
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****************************************************/
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/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
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#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
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#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
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#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
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* Buffer Status
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*/
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#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
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#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
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* Buffer Fault Address
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*/
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#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
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* Buffer 0
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*/
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#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
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* Buffer 1
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*/
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#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
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* Buffer 2
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*/
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#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
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* Lookaside Buffer 3
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*/
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#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
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* Lookaside Buffer 4
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*/
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#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
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* Lookaside Buffer 5
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*/
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#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
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* Lookaside Buffer 6
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*/
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#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
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* Lookaside Buffer 7
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*/
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#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
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* Lookaside Buffer 8
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*/
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#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
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* Lookaside Buffer 9
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*/
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#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
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* Lookaside Buffer 10
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*/
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#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
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* Lookaside Buffer 11
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*/
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#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
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* Lookaside Buffer 12
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*/
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#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
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* Lookaside Buffer 13
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*/
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#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
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* Lookaside Buffer 14
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*/
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#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
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* Lookaside Buffer 15
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*/
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#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
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#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
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#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
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#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
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#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
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#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
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#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
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#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
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#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
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#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
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#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
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#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
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#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
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#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
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#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
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#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
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#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
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#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
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#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
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#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
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/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
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#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
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#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
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#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
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#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
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#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
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#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
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* Protection Lookaside Buffer 0
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*/
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#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
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* Protection Lookaside Buffer 1
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*/
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#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
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* Protection Lookaside Buffer 2
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*/
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#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
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* Protection Lookaside Buffer 3
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*/
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#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
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* Protection Lookaside Buffer 4
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*/
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#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
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* Protection Lookaside Buffer 5
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*/
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#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
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* Protection Lookaside Buffer 6
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*/
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#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
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* Protection Lookaside Buffer 7
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*/
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#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
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* Protection Lookaside Buffer 8
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*/
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#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
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* Protection Lookaside Buffer 9
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*/
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#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
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* Protection Lookaside Buffer 10
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*/
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#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
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* Protection Lookaside Buffer 11
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*/
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#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
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* Protection Lookaside Buffer 12
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*/
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#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
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* Protection Lookaside Buffer 13
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*/
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#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
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* Protection Lookaside Buffer 14
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*/
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#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
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* Protection Lookaside Buffer 15
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*/
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#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
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#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
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#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
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#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
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#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
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#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
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#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
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#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
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#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
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#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
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#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
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#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
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#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
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#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
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#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
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#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
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#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
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#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
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#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
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/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
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#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
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#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
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#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
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#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
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#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
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#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
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#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
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#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
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#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
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#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
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#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
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#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
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#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
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#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
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#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
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#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
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#define IMASK 0xFFE02104 /* Interrupt Mask Register */
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#define IPEND 0xFFE02108 /* Interrupt Pending Register */
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#define ILAT 0xFFE0210C /* Interrupt Latch Register */
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#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
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/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
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#define TCNTL 0xFFE03000 /* Core Timer Control Register */
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#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
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#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
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#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
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/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
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#define DSPID 0xFFE05000 /* DSP Processor ID Register for
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* MP implementations
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*/
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#define DBGSTAT 0xFFE05008 /* Debug Status Register */
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/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
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#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
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#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
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#define TBUF 0xFFE06100 /* Trace Buffer */
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/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
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/* Watchpoint Instruction Address Control Register */
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#define WPIACTL 0xFFE07000
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/* Watchpoint Instruction Address Register 0 */
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#define WPIA0 0xFFE07040
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/* Watchpoint Instruction Address Register 1 */
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#define WPIA1 0xFFE07044
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/* Watchpoint Instruction Address Register 2 */
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#define WPIA2 0xFFE07048
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/* Watchpoint Instruction Address Register 3 */
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#define WPIA3 0xFFE0704C
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/* Watchpoint Instruction Address Register 4 */
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#define WPIA4 0xFFE07050
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/* Watchpoint Instruction Address Register 5 */
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#define WPIA5 0xFFE07054
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/* Watchpoint Instruction Address Count Register 0 */
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#define WPIACNT0 0xFFE07080
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/* Watchpoint Instruction Address Count Register 1 */
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#define WPIACNT1 0xFFE07084
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/* Watchpoint Instruction Address Count Register 2 */
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#define WPIACNT2 0xFFE07088
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/* Watchpoint Instruction Address Count Register 3 */
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#define WPIACNT3 0xFFE0708C
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/* Watchpoint Instruction Address Count Register 4 */
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#define WPIACNT4 0xFFE07090
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/* Watchpoint Instruction Address Count Register 5 */
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#define WPIACNT5 0xFFE07094
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/* Watchpoint Data Address Control Register */
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#define WPDACTL 0xFFE07100
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/* Watchpoint Data Address Register 0 */
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#define WPDA0 0xFFE07140
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/* Watchpoint Data Address Register 1 */
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#define WPDA1 0xFFE07144
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/* Watchpoint Data Address Count Value Register 0 */
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#define WPDACNT0 0xFFE07180
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/* Watchpoint Data Address Count Value Register 1 */
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#define WPDACNT1 0xFFE07184
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/* Watchpoint Status Register */
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#define WPSTAT 0xFFE07200
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/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
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/* Performance Monitor Control Register */
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#define PFCTL 0xFFE08000
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/* Performance Monitor Counter Register 0 */
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#define PFCNTR0 0xFFE08100
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/* Performance Monitor Counter Register 1 */
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#define PFCNTR1 0xFFE08104
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/****************************************************
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* Core MMR Register Bits
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****************************************************/
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/**************************************************
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* EVT registers (ILAT, IMASK, and IPEND).
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**************************************************/
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/* Bit Positions */
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#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
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#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
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#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
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#define EVT_EVX_P 0x00000003 /* Exception bit position */
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#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
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#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
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#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
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#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
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#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
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#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
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#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
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#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
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#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
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#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
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#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
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#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
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/* Masks */
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#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
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#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
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#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
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#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
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#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
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#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
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#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
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#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
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#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
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#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
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#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
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#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
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#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
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#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
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#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
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#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
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/**************************************************
|
|
* DMEM_CONTROL Register
|
|
**************************************************/
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/* Bit Positions */
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#define ENDM_P 0x00 /* (doesn't really exist) Enable
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*Data Memory L1
|
|
*/
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#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
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#define ENDCPLB_P 0x01 /* Enable DCPLBS */
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#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
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#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
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#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
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#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
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#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
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#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
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#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
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|
#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
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|
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/* Masks */
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|
#define ENDM 0x00000001 /* (doesn't really exist) Enable
|
|
* Data Memory L1
|
|
*/
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|
#define ENDCPLB 0x00000002 /* Enable DCPLB */
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#define ASRAM_BSRAM 0x00000000
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|
#define ACACHE_BSRAM 0x00000008
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|
#define ACACHE_BCACHE 0x0000000C
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#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
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#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
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#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
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|
|
|
/* IMEM_CONTROL Register */
|
|
/* Bit Positions */
|
|
#define ENIM_P 0x00 /* Enable L1 Code Memory */
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|
#define IMCTL_ENIM_P 0x00 /* "" (older define) */
|
|
#define ENICPLB_P 0x01 /* Enable ICPLB */
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|
#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
|
|
#define IMC_P 0x02 /* Enable */
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|
#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
|
|
* cache (0=SRAM)
|
|
*/
|
|
#define ILOC0_P 0x03 /* Lock Way 0 */
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|
#define ILOC1_P 0x04 /* Lock Way 1 */
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|
#define ILOC2_P 0x05 /* Lock Way 2 */
|
|
#define ILOC3_P 0x06 /* Lock Way 3 */
|
|
#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
|
|
* Priority
|
|
*/
|
|
/* Masks */
|
|
#define ENIM 0x00000001 /* Enable L1 Code Memory */
|
|
#define ENICPLB 0x00000002 /* Enable ICPLB */
|
|
#define IMC 0x00000004 /* Configure L1 code memory as
|
|
* cache (0=SRAM)
|
|
*/
|
|
#define ILOC0 0x00000008 /* Lock Way 0 */
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|
#define ILOC1 0x00000010 /* Lock Way 1 */
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|
#define ILOC2 0x00000020 /* Lock Way 2 */
|
|
#define ILOC3 0x00000040 /* Lock Way 3 */
|
|
#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
|
|
* Priority
|
|
*/
|
|
|
|
/* TCNTL Masks */
|
|
#define TMPWR 0x00000001 /* Timer Low Power Control,
|
|
* 0=low power mode, 1=active state
|
|
*/
|
|
#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
|
|
#define TAUTORLD 0x00000004 /* Timer auto reload */
|
|
#define TINT 0x00000008 /* Timer generated interrupt 0=no
|
|
* interrupt has been generated,
|
|
* 1=interrupt has been generated
|
|
* (sticky)
|
|
*/
|
|
|
|
/* DCPLB_DATA and ICPLB_DATA Registers */
|
|
/* Bit Positions */
|
|
#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
|
|
#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
|
|
* locked
|
|
*/
|
|
#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
|
|
* allowed (user mode)
|
|
*/
|
|
/* Masks */
|
|
#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
|
|
#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
|
|
* locked
|
|
*/
|
|
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
|
|
* allowed (user mode)
|
|
*/
|
|
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
|
|
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
|
|
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
|
|
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
|
|
#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
|
|
* mapped to L1
|
|
*/
|
|
#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
|
|
* priority port
|
|
*/
|
|
#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
|
|
* in L1
|
|
*/
|
|
/* ICPLB_DATA only */
|
|
#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
|
|
* 1=priority for non-replacement
|
|
*/
|
|
/* DCPLB_DATA only */
|
|
#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
|
|
* access allowed (user mode)
|
|
*/
|
|
#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
|
|
* access allowed (supervisor mode)
|
|
*/
|
|
#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
|
|
#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
|
|
* write-through writes,
|
|
* 1= allocate cache lines on
|
|
* write-through writes.
|
|
*/
|
|
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
|
|
|
|
/* TBUFCTL Masks */
|
|
#define TBUFPWR 0x0001
|
|
#define TBUFEN 0x0002
|
|
#define TBUFOVF 0x0004
|
|
#define TBUFCMPLP_SINGLE 0x0008
|
|
#define TBUFCMPLP_DOUBLE 0x0010
|
|
#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
|
|
|
|
/* TBUFSTAT Masks */
|
|
#define TBUFCNT 0x001F
|
|
|
|
/* ITEST_COMMAND and DTEST_COMMAND Registers */
|
|
/* Masks */
|
|
#define TEST_READ 0x00000000 /* Read Access */
|
|
#define TEST_WRITE 0x00000002 /* Write Access */
|
|
#define TEST_TAG 0x00000000 /* Access TAG */
|
|
#define TEST_DATA 0x00000004 /* Access DATA */
|
|
#define TEST_DW0 0x00000000 /* Select Double Word 0 */
|
|
#define TEST_DW1 0x00000008 /* Select Double Word 1 */
|
|
#define TEST_DW2 0x00000010 /* Select Double Word 2 */
|
|
#define TEST_DW3 0x00000018 /* Select Double Word 3 */
|
|
#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
|
|
#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
|
|
#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
|
|
#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
|
|
#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
|
|
#define TEST_WAY0 0x00000000 /* Access Way0 */
|
|
#define TEST_WAY1 0x04000000 /* Access Way1 */
|
|
/* ITEST_COMMAND only */
|
|
#define TEST_WAY2 0x08000000 /* Access Way2 */
|
|
#define TEST_WAY3 0x0C000000 /* Access Way3 */
|
|
/* DTEST_COMMAND only */
|
|
#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
|
|
#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
|
|
|
|
#endif /* _DEF_LPBLACKFIN_H */
|