3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
119 lines
4.4 KiB
C
119 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_RSC_HW_H_
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#define _SDE_RSC_HW_H_
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#include <linux/kernel.h>
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#include <linux/sde_io_util.h>
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#include <linux/sde_rsc.h>
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/* display rsc offset */
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#define SDE_RSCC_PDC_SEQ_START_ADDR_REG_OFFSET_DRV0 0x020
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#define SDE_RSCC_PDC_MATCH_VALUE_LO_REG_OFFSET_DRV0 0x024
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#define SDE_RSCC_PDC_MATCH_VALUE_HI_REG_OFFSET_DRV0 0x028
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#define SDE_RSCC_PDC_SLAVE_ID_DRV0 0x02c
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#define SDE_RSCC_SEQ_PROGRAM_COUNTER 0x408
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#define SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0 0x410
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#define SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0 0x414
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#define SDE_RSCC_SEQ_MEM_0_DRV0 0x600
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#define SDE_RSCC_SOLVER_OVERRIDE_CTRL_DRV0 0xc14
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#define SDE_RSCC_ERROR_IRQ_STATUS_DRV0 0x0d0
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#define SDE_RSCC_SEQ_BUSY_DRV0 0x404
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#define SDE_RSCC_SOLVER_STATUS0_DRV0 0xc24
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#define SDE_RSCC_SOLVER_STATUS1_DRV0 0xc28
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#define SDE_RSCC_SOLVER_STATUS2_DRV0 0xc2c
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#define SDE_RSCC_AMC_TCS_MODE_IRQ_STATUS_DRV0 0x1c00
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#define SDE_RSCC_SOFT_WAKEUP_TIME_LO_DRV0 0xc04
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#define SDE_RSCC_SOFT_WAKEUP_TIME_HI_DRV0 0xc08
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#define SDE_RSCC_MAX_IDLE_DURATION_DRV0 0xc0c
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#define SDE_RSC_SOLVER_TIME_SLOT_TABLE_0_DRV0 0x1000
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#define SDE_RSC_SOLVER_TIME_SLOT_TABLE_1_DRV0 0x1004
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#define SDE_RSC_SOLVER_TIME_SLOT_TABLE_2_DRV0 0x1008
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#define SDE_RSC_SOLVER_TIME_SLOT_TABLE_3_DRV0 0x100c
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#define SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0 0xc20
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#define SDE_RSC_SOLVER_MODE_PRI_TABLE_SLOT0_PRI0_DRV0 0x1080
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#define SDE_RSC_SOLVER_MODE_PRI_TABLE_SLOT1_PRI0_DRV0 0x1100
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#define SDE_RSC_SOLVER_MODE_PRI_TABLE_SLOT1_PRI3_DRV0 0x110c
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#define SDE_RSC_SOLVER_MODE_PRI_TABLE_SLOT2_PRI0_DRV0 0x1180
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#define SDE_RSC_SOLVER_MODE_PRI_TABLE_SLOT2_PRI3_DRV0 0x118c
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#define SDE_RSC_SOLVER_OVERRIDE_MODE_DRV0 0xc18
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#define SDE_RSC_SOLVER_OVERRIDE_CTRL_DRV0 0xc14
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#define SDE_RSC_TIMERS_CONSIDERED_DRV0 0xc00
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#define SDE_RSC_SOLVER_OVERRIDE_IDLE_TIME_DRV0 0xc1c
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#define SDE_RSC_SOLVER_MODE_PARM0_DRV0_MODE0 0xc30
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#define SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE0 0xc34
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#define SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE0 0xc38
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#define SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE0 0xc40
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#define SDE_RSC_SOLVER_MODE_PARM0_DRV0_MODE1 0xc4c
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#define SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE1 0xc50
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#define SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE1 0xc54
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#define SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE1 0xc5c
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#define SDE_RSC_SOLVER_MODE_PARM0_DRV0_MODE2 0xc68
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#define SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE2 0xc6c
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#define SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE2 0xc70
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#define SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE2 0xc78
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#define SDE_RSCC_TCS_DRV0_CONTROL 0x1c14
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#define SDE_RSCC_WRAPPER_CTRL 0x000
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#define SDE_RSCC_WRAPPER_OVERRIDE_CTRL 0x004
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#define SDE_RSCC_WRAPPER_STATIC_WAKEUP_0 0x008
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#define SDE_RSCC_WRAPPER_RSCC_MODE_THRESHOLD 0x00c
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#define SDE_RSCC_WRAPPER_DEBUG_BUS 0x010
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#define SDE_RSCC_WRAPPER_VSYNC_TIMESTAMP0 0x018
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#define SDE_RSCC_WRAPPER_VSYNC_TIMESTAMP1 0x01c
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#define SDE_RSCC_SPARE_PWR_EVENT 0x020
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#define SDE_RSCC_PWR_CTRL 0x024
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#define SDE_RSCC_WRAPPER_OVERRIDE_CTRL2 0x040
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#define SDE_RSCC_WRAPPER_MODE_MIN_THRESHOLD 0x044
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#define SDE_RSCC_WRAPPER_BW_INDICATION 0x048
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#define SDE_RSCC_WRAPPER_DEBUG_CTRL2 0x050
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/* qtimer offset */
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#define SDE_RSCC_QTMR_AC_HW_FRAME_SEL_1 0x1FE0
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#define SDE_RSCC_QTMR_AC_HW_FRAME_SEL_2 0x1FF0
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#define SDE_RSCC_QTMR_AC_CNTACR0_FG0 0x1040
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#define SDE_RSCC_QTMR_AC_CNTACR1_FG0 0x1044
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#define SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_LO 0x2020
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#define SDE_RSCC_F0_QTMR_V1_CNTP_CVAL_HI 0x2024
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#define SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_LO 0x3020
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#define SDE_RSCC_F1_QTMR_V1_CNTP_CVAL_HI 0x3024
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#define SDE_RSCC_F0_QTMR_V1_CNTP_CTL 0x202C
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#define SDE_RSCC_F1_QTMR_V1_CNTP_CTL 0x302C
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#define MAX_CHECK_LOOPS 500
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#define POWER_CTRL_BIT_12 12
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#define SDE_RSC_MODE_0_VAL 0
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#define SDE_RSC_MODE_1_VAL 1
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#define MAX_MODE2_ENTRY_TRY 3
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int rsc_hw_vsync(struct sde_rsc_priv *rsc, enum rsc_vsync_req request,
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char *buffer, int buffer_size, u32 mode);
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bool rsc_hw_is_amc_mode(struct sde_rsc_priv *rsc);
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void rsc_hw_debug_dump(struct sde_rsc_priv *rsc, u32 mux_sel);
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int sde_rsc_debug_show(struct seq_file *s, struct sde_rsc_priv *rsc);
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int rsc_hw_mode_ctrl(struct sde_rsc_priv *rsc, enum rsc_mode_req request,
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char *buffer, int buffer_size, u32 mode);
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int sde_rsc_mode2_exit(struct sde_rsc_priv *rsc, enum sde_rsc_state state);
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int rsc_hw_tcs_use_ok(struct sde_rsc_priv *rsc);
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int rsc_hw_tcs_wait(struct sde_rsc_priv *rsc);
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#endif /* _SDE_RSC_HW_H_ */
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