Kevin Cernekee 0f334a3e8c MIPS: Fix machine check exception in kmap_coherent() ... On an SMP system with cache aliases, the following sequence of events may happen: 1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a temporary mapping in the fixmap region 2) copy_page() starts on CPU0 3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page() 4) CPU0 takes the interrupt, interrupting copy_page() 5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again 6) The second invocation of kmap_coherent() on CPU0 tries to use the same fixmap virtual address that was being used by copy_user_highpage() 7) CPU0 throws a machine check exception for the TLB address conflict Fixed by creating an extra set of fixmap entries for use in interrupt handlers. This prevents fixmap VA conflicts between copy_user_highpage() running in user context, and local_r4k_flush_cache_page() invoked from an SMP IPI. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2009-11-02 12:00:04 +01:00
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c-octeon.c	cpumask: use mm_cpumask() wrapper: mips	2009-09-24 09:34:51 +09:30
c-r3k.c
c-r4k.c
c-tx39.c
cache.c
cerr-sb1.c
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c
extable.c
fault.c	MIPS: Don't corrupt page tables on vmalloc fault.	2009-09-17 20:07:52 +02:00
highmem.c
hugetlbpage.c
init.c	MIPS: Fix machine check exception in kmap_coherent()	2009-11-02 12:00:04 +01:00
ioremap.c
Makefile
page.c
pgtable-32.c
pgtable-64.c	MIPS: Shrink the size of tlb handler	2009-09-17 20:07:51 +02:00
sc-ip22.c
sc-mips.c	MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.	2009-09-30 21:47:00 +02:00
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c	MIPS: Remove useless zero initializations.	2009-09-17 20:07:51 +02:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: BCM63xx: Add Broadcom 63xx CPU definitions.	2009-09-17 20:07:52 +02:00
uasm.c
uasm.h