Wu Zhangjin 4e73238d16 MIPS: Oprofile: Fix Loongson irq handler ... The interrupt enable bit for the performance counters is in the Control Register $24, not in the counter register. loongson2_perfcount_handler(), we need to use Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1198/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---		2010-05-15 21:59:54 +01:00
..
common.c	MIPS: Simplify the weak annotation with __weak	2010-02-27 12:53:17 +01:00
Makefile
op_impl.h
op_model_loongson2.c	MIPS: Oprofile: Fix Loongson irq handler	2010-05-15 21:59:54 +01:00
op_model_mipsxx.c
op_model_rm9000.c