00d1c5e057
These new controls toggle experimental support for a new CPU feature, the straightforward extension of largepages from the pmd level to the pud level, which allows 1GB (kernel) TLBs instead of 2MB TLBs. Turn it off by default, as this code has not been tested well enough yet. Use the CONFIG_DIRECT_GBPAGES=y .config option or gbpages on the boot line can be used to enable it. If enabled in the .config then nogbpages boot option disables it. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
275 lines
7.7 KiB
C
275 lines
7.7 KiB
C
#ifndef _X86_64_PGTABLE_H
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#define _X86_64_PGTABLE_H
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#include <linux/const.h>
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#ifndef __ASSEMBLY__
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/*
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* This file contains the functions and defines necessary to modify and use
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* the x86-64 page table tree.
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*/
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#include <asm/processor.h>
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#include <linux/bitops.h>
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#include <linux/threads.h>
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#include <asm/pda.h>
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extern pud_t level3_kernel_pgt[512];
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extern pud_t level3_ident_pgt[512];
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extern pmd_t level2_kernel_pgt[512];
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extern pgd_t init_level4_pgt[];
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#define swapper_pg_dir init_level4_pgt
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extern void paging_init(void);
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#endif /* !__ASSEMBLY__ */
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#define SHARED_KERNEL_PMD 1
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/*
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* PGDIR_SHIFT determines what a top-level page table entry can map
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*/
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#define PGDIR_SHIFT 39
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#define PTRS_PER_PGD 512
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/*
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* 3rd level page
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*/
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#define PUD_SHIFT 30
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#define PTRS_PER_PUD 512
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/*
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* PMD_SHIFT determines the size of the area a middle-level
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* page table can map
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*/
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#define PMD_SHIFT 21
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#define PTRS_PER_PMD 512
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/*
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* entries per page directory level
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*/
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#define PTRS_PER_PTE 512
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#ifndef __ASSEMBLY__
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%016lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p(%016lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
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#define pud_ERROR(e) \
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printk("%s:%d: bad pud %p(%016lx).\n", __FILE__, __LINE__, &(e), pud_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%016lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
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#define pgd_none(x) (!pgd_val(x))
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#define pud_none(x) (!pud_val(x))
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struct mm_struct;
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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*ptep = native_make_pte(0);
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}
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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{
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*ptep = pte;
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pte(xchg(&xp->pte, 0));
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#else
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/* native_local_ptep_get_and_clear, but duplicated because of cyclic dependency */
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pte_t ret = *xp;
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native_pte_clear(NULL, 0, xp);
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return ret;
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#endif
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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}
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static inline void native_pmd_clear(pmd_t *pmd)
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{
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native_set_pmd(pmd, native_make_pmd(0));
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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*pudp = pud;
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}
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static inline void native_pud_clear(pud_t *pud)
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{
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native_set_pud(pud, native_make_pud(0));
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}
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static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
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{
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*pgdp = pgd;
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}
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static inline void native_pgd_clear(pgd_t * pgd)
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{
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native_set_pgd(pgd, native_make_pgd(0));
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}
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#define pte_same(a, b) ((a).pte == (b).pte)
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#endif /* !__ASSEMBLY__ */
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#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define MAXMEM _AC(0x3fffffffffff, UL)
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#define VMALLOC_START _AC(0xffffc20000000000, UL)
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#define VMALLOC_END _AC(0xffffe1ffffffffff, UL)
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#define VMEMMAP_START _AC(0xffffe20000000000, UL)
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#define MODULES_VADDR _AC(0xffffffffa0000000, UL)
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#define MODULES_END _AC(0xfffffffffff00000, UL)
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#define MODULES_LEN (MODULES_END - MODULES_VADDR)
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#ifndef __ASSEMBLY__
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static inline unsigned long pgd_bad(pgd_t pgd)
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{
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return pgd_val(pgd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
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}
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static inline unsigned long pud_bad(pud_t pud)
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{
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return pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
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}
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static inline unsigned long pmd_bad(pmd_t pmd)
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{
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return pmd_val(pmd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
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}
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
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#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) /* FIXME: is this right? */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define pte_pfn(x) ((pte_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT))
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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/*
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* Level 4 access.
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*/
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#define pgd_page_vaddr(pgd) ((unsigned long) __va((unsigned long)pgd_val(pgd) & PTE_MASK))
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#define pgd_page(pgd) (pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT))
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
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#define pgd_offset_k(address) (init_level4_pgt + pgd_index(address))
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#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT)
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static inline int pgd_large(pgd_t pgd) { return 0; }
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#define mk_kernel_pgd(address) ((pgd_t){ (address) | _KERNPG_TABLE })
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/* PUD - Level3 access */
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/* to find an entry in a page-table-directory. */
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#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PHYSICAL_PAGE_MASK))
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#define pud_page(pud) (pfn_to_page(pud_val(pud) >> PAGE_SHIFT))
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#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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#define pud_offset(pgd, address) ((pud_t *) pgd_page_vaddr(*(pgd)) + pud_index(address))
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#define pud_present(pud) (pud_val(pud) & _PAGE_PRESENT)
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static inline int pud_large(pud_t pte)
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{
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return (pud_val(pte) & (_PAGE_PSE|_PAGE_PRESENT)) ==
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(_PAGE_PSE|_PAGE_PRESENT);
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}
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/* PMD - Level 2 access */
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#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PTE_MASK))
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#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
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#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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#define pmd_offset(dir, address) ((pmd_t *) pud_page_vaddr(*(dir)) + \
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pmd_index(address))
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
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#define pfn_pmd(nr,prot) (__pmd(((nr) << PAGE_SHIFT) | pgprot_val(prot)))
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#define pmd_pfn(x) ((pmd_val(x) & __PHYSICAL_MASK) >> PAGE_SHIFT)
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#define pte_to_pgoff(pte) ((pte_val(pte) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
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#define pgoff_to_pte(off) ((pte_t) { .pte = ((off) << PAGE_SHIFT) | _PAGE_FILE })
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#define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT
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/* PTE - Level 1 access. */
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/* page, protection -> pte */
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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#define pte_index(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) ((pte_t *) pmd_page_vaddr(*(dir)) + \
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pte_index(address))
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/* x86-64 always has all page tables mapped. */
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#define pte_offset_map(dir,address) pte_offset_kernel(dir,address)
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#define pte_offset_map_nested(dir,address) pte_offset_kernel(dir,address)
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#define pte_unmap(pte) /* NOP */
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#define pte_unmap_nested(pte) /* NOP */
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#define update_mmu_cache(vma,address,pte) do { } while (0)
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extern int direct_gbpages;
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/* Encode and de-code a swap entry */
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#define __swp_type(x) (((x).val >> 1) & 0x3f)
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#define __swp_offset(x) ((x).val >> 8)
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#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
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extern int kern_addr_valid(unsigned long addr);
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extern void cleanup_highmap(void);
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#define pgtable_cache_init() do { } while (0)
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#define check_pgt_cache() do { } while (0)
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#define PAGE_AGP PAGE_KERNEL_NOCACHE
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#define HAVE_PAGE_AGP 1
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/* fs/proc/kcore.c */
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#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
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#define kc_offset_to_vaddr(o) \
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(((o) & (1UL << (__VIRTUAL_MASK_SHIFT-1))) ? ((o) | (~__VIRTUAL_MASK)) : (o))
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#define __HAVE_ARCH_PTE_SAME
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#endif /* !__ASSEMBLY__ */
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#endif /* _X86_64_PGTABLE_H */
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