fc0b7a2036
When CONFIG_PM is selected, the VFP code does not have any handler installed to deal with either saving the VFP state of the current task, nor does it do anything to try and restore the VFP after a resume. On resume, the VFP will have been reset and the co-processor access control registers are in an indeterminate state (very probably the CP10 and CP11 the VFP uses will have been disabled by the ARM core reset). When this happens, resume will break as soon as it tries to unfreeze the tasks and restart scheduling. Add a sys device to allow us to hook the suspend call to save the current thread state if the thread is using VFP and a resume hook which restores the CP10/CP11 access and ensures the VFP is disabled so that the lazy swapping will take place on next access. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
383 lines
9.5 KiB
C
383 lines
9.5 KiB
C
/*
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* linux/arch/arm/vfp/vfp.h
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
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{
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if (shift) {
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if (shift < 32)
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val = val >> shift | ((val << (32 - shift)) != 0);
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else
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val = val != 0;
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}
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return val;
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}
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static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
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{
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if (shift) {
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if (shift < 64)
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val = val >> shift | ((val << (64 - shift)) != 0);
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else
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val = val != 0;
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}
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return val;
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}
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static inline u32 vfp_hi64to32jamming(u64 val)
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{
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u32 v;
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asm(
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"cmp %Q1, #1 @ vfp_hi64to32jamming\n\t"
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"movcc %0, %R1\n\t"
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"orrcs %0, %R1, #1"
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: "=r" (v) : "r" (val) : "cc");
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return v;
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}
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static inline void add128(u64 *resh, u64 *resl, u64 nh, u64 nl, u64 mh, u64 ml)
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{
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asm( "adds %Q0, %Q2, %Q4\n\t"
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"adcs %R0, %R2, %R4\n\t"
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"adcs %Q1, %Q3, %Q5\n\t"
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"adc %R1, %R3, %R5"
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: "=r" (nl), "=r" (nh)
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: "0" (nl), "1" (nh), "r" (ml), "r" (mh)
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: "cc");
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*resh = nh;
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*resl = nl;
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}
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static inline void sub128(u64 *resh, u64 *resl, u64 nh, u64 nl, u64 mh, u64 ml)
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{
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asm( "subs %Q0, %Q2, %Q4\n\t"
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"sbcs %R0, %R2, %R4\n\t"
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"sbcs %Q1, %Q3, %Q5\n\t"
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"sbc %R1, %R3, %R5\n\t"
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: "=r" (nl), "=r" (nh)
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: "0" (nl), "1" (nh), "r" (ml), "r" (mh)
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: "cc");
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*resh = nh;
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*resl = nl;
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}
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static inline void mul64to128(u64 *resh, u64 *resl, u64 n, u64 m)
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{
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u32 nh, nl, mh, ml;
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u64 rh, rma, rmb, rl;
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nl = n;
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ml = m;
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rl = (u64)nl * ml;
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nh = n >> 32;
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rma = (u64)nh * ml;
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mh = m >> 32;
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rmb = (u64)nl * mh;
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rma += rmb;
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rh = (u64)nh * mh;
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rh += ((u64)(rma < rmb) << 32) + (rma >> 32);
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rma <<= 32;
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rl += rma;
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rh += (rl < rma);
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*resl = rl;
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*resh = rh;
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}
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static inline void shift64left(u64 *resh, u64 *resl, u64 n)
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{
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*resh = n >> 63;
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*resl = n << 1;
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}
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static inline u64 vfp_hi64multiply64(u64 n, u64 m)
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{
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u64 rh, rl;
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mul64to128(&rh, &rl, n, m);
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return rh | (rl != 0);
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}
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static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
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{
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u64 mh, ml, remh, reml, termh, terml, z;
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if (nh >= m)
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return ~0ULL;
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mh = m >> 32;
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if (mh << 32 <= nh) {
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z = 0xffffffff00000000ULL;
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} else {
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z = nh;
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do_div(z, mh);
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z <<= 32;
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}
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mul64to128(&termh, &terml, m, z);
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sub128(&remh, &reml, nh, nl, termh, terml);
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ml = m << 32;
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while ((s64)remh < 0) {
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z -= 0x100000000ULL;
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add128(&remh, &reml, remh, reml, mh, ml);
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}
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remh = (remh << 32) | (reml >> 32);
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if (mh << 32 <= remh) {
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z |= 0xffffffff;
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} else {
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do_div(remh, mh);
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z |= remh;
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}
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return z;
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}
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/*
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* Operations on unpacked elements
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*/
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#define vfp_sign_negate(sign) (sign ^ 0x8000)
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/*
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* Single-precision
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*/
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struct vfp_single {
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s16 exponent;
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u16 sign;
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u32 significand;
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};
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extern s32 vfp_get_float(unsigned int reg);
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extern void vfp_put_float(s32 val, unsigned int reg);
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/*
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* VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa
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* VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent
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* VFP_SINGLE_LOW_BITS - number of low bits in the unpacked significand
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* which are not propagated to the float upon packing.
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*/
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#define VFP_SINGLE_MANTISSA_BITS (23)
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#define VFP_SINGLE_EXPONENT_BITS (8)
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#define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2)
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#define VFP_SINGLE_LOW_BITS_MASK ((1 << VFP_SINGLE_LOW_BITS) - 1)
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/*
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* The bit in an unpacked float which indicates that it is a quiet NaN
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*/
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#define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS))
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/*
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* Operations on packed single-precision numbers
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*/
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#define vfp_single_packed_sign(v) ((v) & 0x80000000)
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#define vfp_single_packed_negate(v) ((v) ^ 0x80000000)
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#define vfp_single_packed_abs(v) ((v) & ~0x80000000)
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#define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1))
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#define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1))
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/*
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* Unpack a single-precision float. Note that this returns the magnitude
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* of the single-precision float mantissa with the 1. if necessary,
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* aligned to bit 30.
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*/
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static inline void vfp_single_unpack(struct vfp_single *s, s32 val)
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{
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u32 significand;
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s->sign = vfp_single_packed_sign(val) >> 16,
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s->exponent = vfp_single_packed_exponent(val);
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significand = (u32) val;
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significand = (significand << (32 - VFP_SINGLE_MANTISSA_BITS)) >> 2;
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if (s->exponent && s->exponent != 255)
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significand |= 0x40000000;
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s->significand = significand;
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}
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/*
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* Re-pack a single-precision float. This assumes that the float is
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* already normalised such that the MSB is bit 30, _not_ bit 31.
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*/
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static inline s32 vfp_single_pack(struct vfp_single *s)
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{
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u32 val;
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val = (s->sign << 16) +
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(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
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(s->significand >> VFP_SINGLE_LOW_BITS);
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return (s32)val;
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}
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#define VFP_NUMBER (1<<0)
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#define VFP_ZERO (1<<1)
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#define VFP_DENORMAL (1<<2)
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#define VFP_INFINITY (1<<3)
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#define VFP_NAN (1<<4)
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#define VFP_NAN_SIGNAL (1<<5)
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#define VFP_QNAN (VFP_NAN)
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#define VFP_SNAN (VFP_NAN|VFP_NAN_SIGNAL)
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static inline int vfp_single_type(struct vfp_single *s)
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{
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int type = VFP_NUMBER;
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if (s->exponent == 255) {
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if (s->significand == 0)
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type = VFP_INFINITY;
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else if (s->significand & VFP_SINGLE_SIGNIFICAND_QNAN)
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type = VFP_QNAN;
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else
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type = VFP_SNAN;
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} else if (s->exponent == 0) {
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if (s->significand == 0)
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type |= VFP_ZERO;
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else
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type |= VFP_DENORMAL;
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}
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return type;
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}
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#ifndef DEBUG
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#define vfp_single_normaliseround(sd,vsd,fpscr,except,func) __vfp_single_normaliseround(sd,vsd,fpscr,except)
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u32 __vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions);
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#else
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u32 vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions, const char *func);
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#endif
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/*
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* Double-precision
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*/
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struct vfp_double {
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s16 exponent;
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u16 sign;
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u64 significand;
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};
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/*
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* VFP_REG_ZERO is a special register number for vfp_get_double
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* which returns (double)0.0. This is useful for the compare with
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* zero instructions.
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*/
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#ifdef CONFIG_VFPv3
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#define VFP_REG_ZERO 32
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#else
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#define VFP_REG_ZERO 16
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#endif
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extern u64 vfp_get_double(unsigned int reg);
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extern void vfp_put_double(u64 val, unsigned int reg);
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#define VFP_DOUBLE_MANTISSA_BITS (52)
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#define VFP_DOUBLE_EXPONENT_BITS (11)
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#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2)
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#define VFP_DOUBLE_LOW_BITS_MASK ((1 << VFP_DOUBLE_LOW_BITS) - 1)
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/*
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* The bit in an unpacked double which indicates that it is a quiet NaN
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*/
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#define VFP_DOUBLE_SIGNIFICAND_QNAN (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS))
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/*
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* Operations on packed single-precision numbers
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*/
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#define vfp_double_packed_sign(v) ((v) & (1ULL << 63))
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#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63))
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#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63))
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#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
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#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
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/*
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* Unpack a double-precision float. Note that this returns the magnitude
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* of the double-precision float mantissa with the 1. if necessary,
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* aligned to bit 62.
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*/
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static inline void vfp_double_unpack(struct vfp_double *s, s64 val)
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{
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u64 significand;
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s->sign = vfp_double_packed_sign(val) >> 48;
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s->exponent = vfp_double_packed_exponent(val);
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significand = (u64) val;
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significand = (significand << (64 - VFP_DOUBLE_MANTISSA_BITS)) >> 2;
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if (s->exponent && s->exponent != 2047)
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significand |= (1ULL << 62);
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s->significand = significand;
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}
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/*
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* Re-pack a double-precision float. This assumes that the float is
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* already normalised such that the MSB is bit 30, _not_ bit 31.
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*/
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static inline s64 vfp_double_pack(struct vfp_double *s)
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{
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u64 val;
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val = ((u64)s->sign << 48) +
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((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
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(s->significand >> VFP_DOUBLE_LOW_BITS);
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return (s64)val;
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}
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static inline int vfp_double_type(struct vfp_double *s)
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{
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int type = VFP_NUMBER;
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if (s->exponent == 2047) {
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if (s->significand == 0)
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type = VFP_INFINITY;
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else if (s->significand & VFP_DOUBLE_SIGNIFICAND_QNAN)
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type = VFP_QNAN;
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else
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type = VFP_SNAN;
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} else if (s->exponent == 0) {
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if (s->significand == 0)
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type |= VFP_ZERO;
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else
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type |= VFP_DENORMAL;
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}
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return type;
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}
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u32 vfp_double_normaliseround(int dd, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func);
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u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
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/*
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* A special flag to tell the normalisation code not to normalise.
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*/
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#define VFP_NAN_FLAG 0x100
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/*
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* A bit pattern used to indicate the initial (unset) value of the
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* exception mask, in case nothing handles an instruction. This
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* doesn't include the NAN flag, which get masked out before
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* we check for an error.
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*/
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#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
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/*
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* A flag to tell vfp instruction type.
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* OP_SCALAR - this operation always operates in scalar mode
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* OP_SD - the instruction exceptionally writes to a single precision result.
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* OP_DD - the instruction exceptionally writes to a double precision result.
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* OP_SM - the instruction exceptionally reads from a single precision operand.
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*/
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#define OP_SCALAR (1 << 0)
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#define OP_SD (1 << 1)
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#define OP_DD (1 << 1)
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#define OP_SM (1 << 2)
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struct op {
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u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
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u32 flags;
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};
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#if defined(CONFIG_SMP) || defined(CONFIG_PM)
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extern void vfp_save_state(void *location, u32 fpexc);
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#endif
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