a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
792 lines
22 KiB
C
792 lines
22 KiB
C
/*
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* at91-ssc.c -- ALSA SoC AT91 SSC Audio Layer Platform driver
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*
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* Author: Frank Mandarino <fmandarino@endrelia.com>
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* Endrelia Technologies Inc.
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*
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* Based on pxa2xx Platform drivers by
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* Liam Girdwood <liam.girdwood@wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/atmel_pdc.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <mach/hardware.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_ssc.h>
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#include "at91-pcm.h"
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#include "at91-ssc.h"
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#if 0
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#define DBG(x...) printk(KERN_DEBUG "at91-ssc:" x)
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#else
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#define DBG(x...)
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#endif
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#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
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#define NUM_SSC_DEVICES 1
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#else
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#define NUM_SSC_DEVICES 3
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#endif
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/*
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* SSC PDC registers required by the PCM DMA engine.
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*/
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static struct at91_pdc_regs pdc_tx_reg = {
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.xpr = ATMEL_PDC_TPR,
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.xcr = ATMEL_PDC_TCR,
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.xnpr = ATMEL_PDC_TNPR,
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.xncr = ATMEL_PDC_TNCR,
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};
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static struct at91_pdc_regs pdc_rx_reg = {
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.xpr = ATMEL_PDC_RPR,
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.xcr = ATMEL_PDC_RCR,
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.xnpr = ATMEL_PDC_RNPR,
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.xncr = ATMEL_PDC_RNCR,
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};
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/*
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* SSC & PDC status bits for transmit and receive.
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*/
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static struct at91_ssc_mask ssc_tx_mask = {
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.ssc_enable = AT91_SSC_TXEN,
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.ssc_disable = AT91_SSC_TXDIS,
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.ssc_endx = AT91_SSC_ENDTX,
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.ssc_endbuf = AT91_SSC_TXBUFE,
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.pdc_enable = ATMEL_PDC_TXTEN,
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.pdc_disable = ATMEL_PDC_TXTDIS,
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};
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static struct at91_ssc_mask ssc_rx_mask = {
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.ssc_enable = AT91_SSC_RXEN,
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.ssc_disable = AT91_SSC_RXDIS,
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.ssc_endx = AT91_SSC_ENDRX,
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.ssc_endbuf = AT91_SSC_RXBUFF,
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.pdc_enable = ATMEL_PDC_RXTEN,
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.pdc_disable = ATMEL_PDC_RXTDIS,
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};
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/*
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* DMA parameters.
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*/
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static struct at91_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
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{{
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.name = "SSC0 PCM out",
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.pdc = &pdc_tx_reg,
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.mask = &ssc_tx_mask,
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},
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{
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.name = "SSC0 PCM in",
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.pdc = &pdc_rx_reg,
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.mask = &ssc_rx_mask,
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}},
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#if NUM_SSC_DEVICES == 3
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{{
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.name = "SSC1 PCM out",
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.pdc = &pdc_tx_reg,
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.mask = &ssc_tx_mask,
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},
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{
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.name = "SSC1 PCM in",
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.pdc = &pdc_rx_reg,
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.mask = &ssc_rx_mask,
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}},
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{{
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.name = "SSC2 PCM out",
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.pdc = &pdc_tx_reg,
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.mask = &ssc_tx_mask,
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},
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{
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.name = "SSC2 PCM in",
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.pdc = &pdc_rx_reg,
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.mask = &ssc_rx_mask,
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}},
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#endif
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};
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struct at91_ssc_state {
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u32 ssc_cmr;
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u32 ssc_rcmr;
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u32 ssc_rfmr;
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u32 ssc_tcmr;
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u32 ssc_tfmr;
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u32 ssc_sr;
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u32 ssc_imr;
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};
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static struct at91_ssc_info {
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char *name;
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struct at91_ssc_periph ssc;
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spinlock_t lock; /* lock for dir_mask */
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unsigned short dir_mask; /* 0=unused, 1=playback, 2=capture */
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unsigned short initialized; /* 1=SSC has been initialized */
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unsigned short daifmt;
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unsigned short cmr_div;
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unsigned short tcmr_period;
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unsigned short rcmr_period;
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struct at91_pcm_dma_params *dma_params[2];
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struct at91_ssc_state ssc_state;
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} ssc_info[NUM_SSC_DEVICES] = {
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{
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.name = "ssc0",
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.lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
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.dir_mask = 0,
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.initialized = 0,
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},
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#if NUM_SSC_DEVICES == 3
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{
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.name = "ssc1",
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.lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
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.dir_mask = 0,
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.initialized = 0,
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},
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{
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.name = "ssc2",
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.lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
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.dir_mask = 0,
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.initialized = 0,
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},
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#endif
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};
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static unsigned int at91_ssc_sysclk;
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/*
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* SSC interrupt handler. Passes PDC interrupts to the DMA
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* interrupt handler in the PCM driver.
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*/
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static irqreturn_t at91_ssc_interrupt(int irq, void *dev_id)
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{
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struct at91_ssc_info *ssc_p = dev_id;
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struct at91_pcm_dma_params *dma_params;
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u32 ssc_sr;
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int i;
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ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR)
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& at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
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/*
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* Loop through the substreams attached to this SSC. If
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* a DMA-related interrupt occurred on that substream, call
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* the DMA interrupt handler function, if one has been
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* registered in the dma_params structure by the PCM driver.
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*/
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for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
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dma_params = ssc_p->dma_params[i];
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if (dma_params != NULL && dma_params->dma_intr_handler != NULL &&
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(ssc_sr &
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(dma_params->mask->ssc_endx | dma_params->mask->ssc_endbuf)))
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dma_params->dma_intr_handler(ssc_sr, dma_params->substream);
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}
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return IRQ_HANDLED;
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}
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/*
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* Startup. Only that one substream allowed in each direction.
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*/
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static int at91_ssc_startup(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
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int dir_mask;
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DBG("ssc_startup: SSC_SR=0x%08lx\n",
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at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
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dir_mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0x1 : 0x2;
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spin_lock_irq(&ssc_p->lock);
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if (ssc_p->dir_mask & dir_mask) {
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spin_unlock_irq(&ssc_p->lock);
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return -EBUSY;
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}
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ssc_p->dir_mask |= dir_mask;
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spin_unlock_irq(&ssc_p->lock);
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return 0;
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}
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/*
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* Shutdown. Clear DMA parameters and shutdown the SSC if there
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* are no other substreams open.
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*/
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static void at91_ssc_shutdown(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
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struct at91_pcm_dma_params *dma_params;
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int dir, dir_mask;
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dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
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dma_params = ssc_p->dma_params[dir];
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if (dma_params != NULL) {
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at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
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dma_params->mask->ssc_disable);
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DBG("%s disabled SSC_SR=0x%08lx\n", (dir ? "receive" : "transmit"),
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at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
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dma_params->ssc_base = NULL;
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dma_params->substream = NULL;
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ssc_p->dma_params[dir] = NULL;
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}
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dir_mask = 1 << dir;
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spin_lock_irq(&ssc_p->lock);
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ssc_p->dir_mask &= ~dir_mask;
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if (!ssc_p->dir_mask) {
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/* Shutdown the SSC clock. */
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DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
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at91_sys_write(AT91_PMC_PCDR, 1<<ssc_p->ssc.pid);
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if (ssc_p->initialized) {
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free_irq(ssc_p->ssc.pid, ssc_p);
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ssc_p->initialized = 0;
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}
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/* Reset the SSC */
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at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
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/* Clear the SSC dividers */
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ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
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}
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spin_unlock_irq(&ssc_p->lock);
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}
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/*
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* Record the SSC system clock rate.
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*/
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static int at91_ssc_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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/*
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* The only clock supplied to the SSC is the AT91 master clock,
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* which is only used if the SSC is generating BCLK and/or
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* LRC clocks.
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*/
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switch (clk_id) {
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case AT91_SYSCLK_MCK:
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at91_ssc_sysclk = freq;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Record the DAI format for use in hw_params().
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*/
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static int at91_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct at91_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
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ssc_p->daifmt = fmt;
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return 0;
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}
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/*
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* Record SSC clock dividers for use in hw_params().
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*/
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static int at91_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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struct at91_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
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switch (div_id) {
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case AT91SSC_CMR_DIV:
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/*
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* The same master clock divider is used for both
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* transmit and receive, so if a value has already
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* been set, it must match this value.
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*/
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if (ssc_p->cmr_div == 0)
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ssc_p->cmr_div = div;
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else
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if (div != ssc_p->cmr_div)
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return -EBUSY;
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break;
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case AT91SSC_TCMR_PERIOD:
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ssc_p->tcmr_period = div;
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break;
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case AT91SSC_RCMR_PERIOD:
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ssc_p->rcmr_period = div;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Configure the SSC.
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*/
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static int at91_ssc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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int id = rtd->dai->cpu_dai->id;
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struct at91_ssc_info *ssc_p = &ssc_info[id];
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struct at91_pcm_dma_params *dma_params;
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int dir, channels, bits;
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u32 tfmr, rfmr, tcmr, rcmr;
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int start_event;
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int ret;
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/*
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* Currently, there is only one set of dma params for
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* each direction. If more are added, this code will
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* have to be changed to select the proper set.
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*/
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dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
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dma_params = &ssc_dma_params[id][dir];
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dma_params->ssc_base = ssc_p->ssc.base;
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dma_params->substream = substream;
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ssc_p->dma_params[dir] = dma_params;
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/*
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* The cpu_dai->dma_data field is only used to communicate the
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* appropriate DMA parameters to the pcm driver hw_params()
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* function. It should not be used for other purposes
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* as it is common to all substreams.
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*/
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rtd->dai->cpu_dai->dma_data = dma_params;
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channels = params_channels(params);
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/*
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* Determine sample size in bits and the PDC increment.
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*/
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switch(params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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bits = 8;
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dma_params->pdc_xfer_size = 1;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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bits = 16;
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dma_params->pdc_xfer_size = 2;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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bits = 24;
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dma_params->pdc_xfer_size = 4;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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bits = 32;
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dma_params->pdc_xfer_size = 4;
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break;
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default:
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printk(KERN_WARNING "at91-ssc: unsupported PCM format");
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return -EINVAL;
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}
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/*
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* The SSC only supports up to 16-bit samples in I2S format, due
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* to the size of the Frame Mode Register FSLEN field.
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*/
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if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
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&& bits > 16) {
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printk(KERN_WARNING
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"at91-ssc: sample size %d is too large for I2S\n", bits);
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return -EINVAL;
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}
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/*
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* Compute SSC register settings.
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*/
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switch (ssc_p->daifmt
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& (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
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/*
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* I2S format, SSC provides BCLK and LRC clocks.
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*
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* The SSC transmit and receive clocks are generated from the
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* MCK divider, and the BCLK signal is output on the SSC TK line.
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*/
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rcmr = (( ssc_p->rcmr_period << 24) & AT91_SSC_PERIOD)
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| (( 1 << 16) & AT91_SSC_STTDLY)
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| (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
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| (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
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| (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
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| (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
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rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
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| (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
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| (((bits - 1) << 16) & AT91_SSC_FSLEN)
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| (((channels - 1) << 8) & AT91_SSC_DATNB)
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| (( 1 << 7) & AT91_SSC_MSBF)
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| (( 0 << 5) & AT91_SSC_LOOP)
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| (((bits - 1) << 0) & AT91_SSC_DATALEN);
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tcmr = (( ssc_p->tcmr_period << 24) & AT91_SSC_PERIOD)
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| (( 1 << 16) & AT91_SSC_STTDLY)
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| (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
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| (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
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| (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO)
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| (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
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tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
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| (( 0 << 23) & AT91_SSC_FSDEN)
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| (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
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| (((bits - 1) << 16) & AT91_SSC_FSLEN)
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| (((channels - 1) << 8) & AT91_SSC_DATNB)
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| (( 1 << 7) & AT91_SSC_MSBF)
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| (( 0 << 5) & AT91_SSC_DATDEF)
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| (((bits - 1) << 0) & AT91_SSC_DATALEN);
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break;
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
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/*
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* I2S format, CODEC supplies BCLK and LRC clocks.
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*
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* The SSC transmit clock is obtained from the BCLK signal on
|
|
* on the TK line, and the SSC receive clock is generated from the
|
|
* transmit clock.
|
|
*
|
|
* For single channel data, one sample is transferred on the falling
|
|
* edge of the LRC clock. For two channel data, one sample is
|
|
* transferred on both edges of the LRC clock.
|
|
*/
|
|
start_event = channels == 1
|
|
? AT91_SSC_START_FALLING_RF
|
|
: AT91_SSC_START_EDGE_RF;
|
|
|
|
rcmr = (( 0 << 24) & AT91_SSC_PERIOD)
|
|
| (( 1 << 16) & AT91_SSC_STTDLY)
|
|
| (( start_event ) & AT91_SSC_START)
|
|
| (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
|
|
| (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
|
|
| (( AT91_SSC_CKS_CLOCK ) & AT91_SSC_CKS);
|
|
|
|
rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
|
|
| (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
|
|
| (( 0 << 16) & AT91_SSC_FSLEN)
|
|
| (( 0 << 8) & AT91_SSC_DATNB)
|
|
| (( 1 << 7) & AT91_SSC_MSBF)
|
|
| (( 0 << 5) & AT91_SSC_LOOP)
|
|
| (((bits - 1) << 0) & AT91_SSC_DATALEN);
|
|
|
|
tcmr = (( 0 << 24) & AT91_SSC_PERIOD)
|
|
| (( 1 << 16) & AT91_SSC_STTDLY)
|
|
| (( start_event ) & AT91_SSC_START)
|
|
| (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
|
|
| (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
|
|
| (( AT91_SSC_CKS_PIN ) & AT91_SSC_CKS);
|
|
|
|
tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
|
|
| (( 0 << 23) & AT91_SSC_FSDEN)
|
|
| (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
|
|
| (( 0 << 16) & AT91_SSC_FSLEN)
|
|
| (( 0 << 8) & AT91_SSC_DATNB)
|
|
| (( 1 << 7) & AT91_SSC_MSBF)
|
|
| (( 0 << 5) & AT91_SSC_DATDEF)
|
|
| (((bits - 1) << 0) & AT91_SSC_DATALEN);
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
|
|
/*
|
|
* DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
|
|
*
|
|
* The SSC transmit and receive clocks are generated from the
|
|
* MCK divider, and the BCLK signal is output on the SSC TK line.
|
|
*/
|
|
rcmr = (( ssc_p->rcmr_period << 24) & AT91_SSC_PERIOD)
|
|
| (( 1 << 16) & AT91_SSC_STTDLY)
|
|
| (( AT91_SSC_START_RISING_RF ) & AT91_SSC_START)
|
|
| (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
|
|
| (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
|
|
| (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
|
|
|
|
rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
|
|
| (( AT91_SSC_FSOS_POSITIVE ) & AT91_SSC_FSOS)
|
|
| (( 0 << 16) & AT91_SSC_FSLEN)
|
|
| (((channels - 1) << 8) & AT91_SSC_DATNB)
|
|
| (( 1 << 7) & AT91_SSC_MSBF)
|
|
| (( 0 << 5) & AT91_SSC_LOOP)
|
|
| (((bits - 1) << 0) & AT91_SSC_DATALEN);
|
|
|
|
tcmr = (( ssc_p->tcmr_period << 24) & AT91_SSC_PERIOD)
|
|
| (( 1 << 16) & AT91_SSC_STTDLY)
|
|
| (( AT91_SSC_START_RISING_RF ) & AT91_SSC_START)
|
|
| (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
|
|
| (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO)
|
|
| (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
|
|
|
|
tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
|
|
| (( 0 << 23) & AT91_SSC_FSDEN)
|
|
| (( AT91_SSC_FSOS_POSITIVE ) & AT91_SSC_FSOS)
|
|
| (( 0 << 16) & AT91_SSC_FSLEN)
|
|
| (((channels - 1) << 8) & AT91_SSC_DATNB)
|
|
| (( 1 << 7) & AT91_SSC_MSBF)
|
|
| (( 0 << 5) & AT91_SSC_DATDEF)
|
|
| (((bits - 1) << 0) & AT91_SSC_DATALEN);
|
|
|
|
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
|
|
default:
|
|
printk(KERN_WARNING "at91-ssc: unsupported DAI format 0x%x.\n",
|
|
ssc_p->daifmt);
|
|
return -EINVAL;
|
|
break;
|
|
}
|
|
DBG("RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr, rfmr, tcmr, tfmr);
|
|
|
|
if (!ssc_p->initialized) {
|
|
|
|
/* Enable PMC peripheral clock for this SSC */
|
|
DBG("Starting pid %d clock\n", ssc_p->ssc.pid);
|
|
at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);
|
|
|
|
/* Reset the SSC and its PDC registers */
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
|
|
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RPR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RCR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNPR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNCR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TPR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TCR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNPR, 0);
|
|
at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNCR, 0);
|
|
|
|
if ((ret = request_irq(ssc_p->ssc.pid, at91_ssc_interrupt,
|
|
0, ssc_p->name, ssc_p)) < 0) {
|
|
printk(KERN_WARNING "at91-ssc: request_irq failure\n");
|
|
|
|
DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
|
|
at91_sys_write(AT91_PMC_PCDR, 1<<ssc_p->ssc.pid);
|
|
return ret;
|
|
}
|
|
|
|
ssc_p->initialized = 1;
|
|
}
|
|
|
|
/* set SSC clock mode register */
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->cmr_div);
|
|
|
|
/* set receive clock mode and format */
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, rcmr);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, rfmr);
|
|
|
|
/* set transmit clock mode and format */
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, tcmr);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, tfmr);
|
|
|
|
DBG("hw_params: SSC initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int at91_ssc_prepare(struct snd_pcm_substream *substream)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
|
|
struct at91_pcm_dma_params *dma_params;
|
|
int dir;
|
|
|
|
dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
|
|
dma_params = ssc_p->dma_params[dir];
|
|
|
|
at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
|
|
dma_params->mask->ssc_enable);
|
|
|
|
DBG("%s enabled SSC_SR=0x%08lx\n", dir ? "receive" : "transmit",
|
|
at91_ssc_read(dma_params->ssc_base + AT91_SSC_SR));
|
|
return 0;
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
static int at91_ssc_suspend(struct platform_device *pdev,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct at91_ssc_info *ssc_p;
|
|
|
|
if(!cpu_dai->active)
|
|
return 0;
|
|
|
|
ssc_p = &ssc_info[cpu_dai->id];
|
|
|
|
/* Save the status register before disabling transmit and receive. */
|
|
ssc_p->ssc_state.ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
|
|
AT91_SSC_TXDIS | AT91_SSC_RXDIS);
|
|
|
|
/* Save the current interrupt mask, then disable unmasked interrupts. */
|
|
ssc_p->ssc_state.ssc_imr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IDR, ssc_p->ssc_state.ssc_imr);
|
|
|
|
ssc_p->ssc_state.ssc_cmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_CMR);
|
|
ssc_p->ssc_state.ssc_rcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
|
|
ssc_p->ssc_state.ssc_rfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RFMR);
|
|
ssc_p->ssc_state.ssc_tcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TCMR);
|
|
ssc_p->ssc_state.ssc_tfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TFMR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int at91_ssc_resume(struct platform_device *pdev,
|
|
struct snd_soc_dai *cpu_dai)
|
|
{
|
|
struct at91_ssc_info *ssc_p;
|
|
|
|
if(!cpu_dai->active)
|
|
return 0;
|
|
|
|
ssc_p = &ssc_info[cpu_dai->id];
|
|
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, ssc_p->ssc_state.ssc_tfmr);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, ssc_p->ssc_state.ssc_tcmr);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, ssc_p->ssc_state.ssc_rfmr);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_rcmr);
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->ssc_state.ssc_cmr);
|
|
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IER, ssc_p->ssc_state.ssc_imr);
|
|
|
|
at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
|
|
((ssc_p->ssc_state.ssc_sr & AT91_SSC_RXENA) ? AT91_SSC_RXEN : 0) |
|
|
((ssc_p->ssc_state.ssc_sr & AT91_SSC_TXENA) ? AT91_SSC_TXEN : 0));
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define at91_ssc_suspend NULL
|
|
#define at91_ssc_resume NULL
|
|
#endif
|
|
|
|
#define AT91_SSC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
|
|
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
|
|
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
|
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
|
|
SNDRV_PCM_RATE_96000)
|
|
|
|
#define AT91_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
|
|
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
struct snd_soc_dai at91_ssc_dai[NUM_SSC_DEVICES] = {
|
|
{ .name = "at91-ssc0",
|
|
.id = 0,
|
|
.type = SND_SOC_DAI_PCM,
|
|
.suspend = at91_ssc_suspend,
|
|
.resume = at91_ssc_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AT91_SSC_RATES,
|
|
.formats = AT91_SSC_FORMATS,},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AT91_SSC_RATES,
|
|
.formats = AT91_SSC_FORMATS,},
|
|
.ops = {
|
|
.startup = at91_ssc_startup,
|
|
.shutdown = at91_ssc_shutdown,
|
|
.prepare = at91_ssc_prepare,
|
|
.hw_params = at91_ssc_hw_params,},
|
|
.dai_ops = {
|
|
.set_sysclk = at91_ssc_set_dai_sysclk,
|
|
.set_fmt = at91_ssc_set_dai_fmt,
|
|
.set_clkdiv = at91_ssc_set_dai_clkdiv,},
|
|
.private_data = &ssc_info[0].ssc,
|
|
},
|
|
#if NUM_SSC_DEVICES == 3
|
|
{ .name = "at91-ssc1",
|
|
.id = 1,
|
|
.type = SND_SOC_DAI_PCM,
|
|
.suspend = at91_ssc_suspend,
|
|
.resume = at91_ssc_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AT91_SSC_RATES,
|
|
.formats = AT91_SSC_FORMATS,},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AT91_SSC_RATES,
|
|
.formats = AT91_SSC_FORMATS,},
|
|
.ops = {
|
|
.startup = at91_ssc_startup,
|
|
.shutdown = at91_ssc_shutdown,
|
|
.prepare = at91_ssc_prepare,
|
|
.hw_params = at91_ssc_hw_params,},
|
|
.dai_ops = {
|
|
.set_sysclk = at91_ssc_set_dai_sysclk,
|
|
.set_fmt = at91_ssc_set_dai_fmt,
|
|
.set_clkdiv = at91_ssc_set_dai_clkdiv,},
|
|
.private_data = &ssc_info[1].ssc,
|
|
},
|
|
{ .name = "at91-ssc2",
|
|
.id = 2,
|
|
.type = SND_SOC_DAI_PCM,
|
|
.suspend = at91_ssc_suspend,
|
|
.resume = at91_ssc_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AT91_SSC_RATES,
|
|
.formats = AT91_SSC_FORMATS,},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AT91_SSC_RATES,
|
|
.formats = AT91_SSC_FORMATS,},
|
|
.ops = {
|
|
.startup = at91_ssc_startup,
|
|
.shutdown = at91_ssc_shutdown,
|
|
.prepare = at91_ssc_prepare,
|
|
.hw_params = at91_ssc_hw_params,},
|
|
.dai_ops = {
|
|
.set_sysclk = at91_ssc_set_dai_sysclk,
|
|
.set_fmt = at91_ssc_set_dai_fmt,
|
|
.set_clkdiv = at91_ssc_set_dai_clkdiv,},
|
|
.private_data = &ssc_info[2].ssc,
|
|
},
|
|
#endif
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(at91_ssc_dai);
|
|
|
|
/* Module information */
|
|
MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com");
|
|
MODULE_DESCRIPTION("AT91 SSC ASoC Interface");
|
|
MODULE_LICENSE("GPL");
|