0d3e865b26
Definitions of UV MMRs. Note: this file is auto-generated by hardware design tools. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
374 lines
16 KiB
C
374 lines
16 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV MMR definitions
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*
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* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef __ASM_X86_UV_MMRS__
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#define __ASM_X86_UV_MMRS__
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/*
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* AUTO GENERATED - Do not edit
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*/
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#define UV_MMR_ENABLE (1UL << 63)
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/* ========================================================================= */
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/* UVH_IPI_INT */
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/* ========================================================================= */
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#define UVH_IPI_INT 0x60500UL
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#define UVH_IPI_INT_32 0x0360
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#define UVH_IPI_INT_VECTOR_SHFT 0
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#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
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#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
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#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
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#define UVH_IPI_INT_DESTMODE_SHFT 11
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#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
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#define UVH_IPI_INT_APIC_ID_SHFT 16
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#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
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#define UVH_IPI_INT_SEND_SHFT 63
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#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
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union uvh_ipi_int_u {
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unsigned long v;
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struct uvh_ipi_int_s {
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unsigned long vector_ : 8; /* RW */
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unsigned long delivery_mode : 3; /* RW */
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unsigned long destmode : 1; /* RW */
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unsigned long rsvd_12_15 : 4; /* */
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unsigned long apic_id : 32; /* RW */
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unsigned long rsvd_48_62 : 15; /* */
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unsigned long send : 1; /* WP */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
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/* ========================================================================= */
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009f0
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
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union uvh_lb_bau_intd_payload_queue_first_u {
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unsigned long v;
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struct uvh_lb_bau_intd_payload_queue_first_s {
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unsigned long rsvd_0_3: 4; /* */
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unsigned long address : 39; /* RW */
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unsigned long rsvd_43_48: 6; /* */
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unsigned long node_id : 14; /* RW */
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unsigned long rsvd_63 : 1; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
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/* ========================================================================= */
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009f8
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
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union uvh_lb_bau_intd_payload_queue_last_u {
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unsigned long v;
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struct uvh_lb_bau_intd_payload_queue_last_s {
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unsigned long rsvd_0_3: 4; /* */
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unsigned long address : 39; /* RW */
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unsigned long rsvd_43_63: 21; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
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/* ========================================================================= */
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x00a00
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
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#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
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union uvh_lb_bau_intd_payload_queue_tail_u {
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unsigned long v;
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struct uvh_lb_bau_intd_payload_queue_tail_s {
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unsigned long rsvd_0_3: 4; /* */
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unsigned long address : 39; /* RW */
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unsigned long rsvd_43_63: 21; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
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/* ========================================================================= */
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
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union uvh_lb_bau_intd_software_acknowledge_u {
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unsigned long v;
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struct uvh_lb_bau_intd_software_acknowledge_s {
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unsigned long pending_0 : 1; /* RW, W1C */
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unsigned long pending_1 : 1; /* RW, W1C */
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unsigned long pending_2 : 1; /* RW, W1C */
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unsigned long pending_3 : 1; /* RW, W1C */
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unsigned long pending_4 : 1; /* RW, W1C */
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unsigned long pending_5 : 1; /* RW, W1C */
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unsigned long pending_6 : 1; /* RW, W1C */
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unsigned long pending_7 : 1; /* RW, W1C */
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unsigned long timeout_0 : 1; /* RW, W1C */
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unsigned long timeout_1 : 1; /* RW, W1C */
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unsigned long timeout_2 : 1; /* RW, W1C */
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unsigned long timeout_3 : 1; /* RW, W1C */
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unsigned long timeout_4 : 1; /* RW, W1C */
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unsigned long timeout_5 : 1; /* RW, W1C */
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unsigned long timeout_6 : 1; /* RW, W1C */
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unsigned long timeout_7 : 1; /* RW, W1C */
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unsigned long rsvd_16_63: 48; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
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/* ========================================================================= */
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#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
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/* ========================================================================= */
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/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
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/* ========================================================================= */
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009d8
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
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#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
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union uvh_lb_bau_sb_activation_control_u {
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unsigned long v;
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struct uvh_lb_bau_sb_activation_control_s {
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unsigned long index : 6; /* RW */
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unsigned long rsvd_6_61: 56; /* */
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unsigned long push : 1; /* WP */
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unsigned long init : 1; /* WP */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
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/* ========================================================================= */
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009e0
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
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union uvh_lb_bau_sb_activation_status_0_u {
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unsigned long v;
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struct uvh_lb_bau_sb_activation_status_0_s {
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unsigned long status : 64; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
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/* ========================================================================= */
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009e8
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
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#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
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union uvh_lb_bau_sb_activation_status_1_u {
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unsigned long v;
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struct uvh_lb_bau_sb_activation_status_1_s {
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unsigned long status : 64; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
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/* ========================================================================= */
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#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
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#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009d0
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#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
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#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
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#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
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#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
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union uvh_lb_bau_sb_descriptor_base_u {
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unsigned long v;
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struct uvh_lb_bau_sb_descriptor_base_s {
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unsigned long rsvd_0_11 : 12; /* */
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unsigned long page_address : 31; /* RW */
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unsigned long rsvd_43_48 : 6; /* */
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unsigned long node_id : 14; /* RW */
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unsigned long rsvd_63 : 1; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_NODE_ID */
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/* ========================================================================= */
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#define UVH_NODE_ID 0x0UL
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#define UVH_NODE_ID_FORCE1_SHFT 0
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#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
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#define UVH_NODE_ID_MANUFACTURER_SHFT 1
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#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
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#define UVH_NODE_ID_PART_NUMBER_SHFT 12
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#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
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#define UVH_NODE_ID_REVISION_SHFT 28
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#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
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#define UVH_NODE_ID_NODE_ID_SHFT 32
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#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
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#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
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#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
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#define UVH_NODE_ID_NI_PORT_SHFT 56
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#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
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union uvh_node_id_u {
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unsigned long v;
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struct uvh_node_id_s {
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unsigned long force1 : 1; /* RO */
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unsigned long manufacturer : 11; /* RO */
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unsigned long part_number : 16; /* RO */
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unsigned long revision : 4; /* RO */
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unsigned long node_id : 15; /* RW */
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unsigned long rsvd_47 : 1; /* */
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unsigned long nodes_per_bit : 7; /* RW */
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unsigned long rsvd_55 : 1; /* */
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unsigned long ni_port : 4; /* RO */
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unsigned long rsvd_60_63 : 4; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_gru_overlay_config_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_gru_overlay_config_mmr_s {
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unsigned long rsvd_0_27: 28; /* */
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unsigned long base : 18; /* RW */
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unsigned long gr4 : 1; /* RW */
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unsigned long rsvd_47_51: 5; /* */
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unsigned long n_gru : 4; /* RW */
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unsigned long rsvd_56_62: 7; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_mmr_overlay_config_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_mmr_overlay_config_mmr_s {
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unsigned long rsvd_0_25: 26; /* */
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unsigned long base : 20; /* RW */
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unsigned long dual_hub : 1; /* RW */
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unsigned long rsvd_47_62: 16; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RTC */
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/* ========================================================================= */
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#define UVH_RTC 0x28000UL
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#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
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#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
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union uvh_rtc_u {
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unsigned long v;
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struct uvh_rtc_s {
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unsigned long real_time_clock : 56; /* RW */
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unsigned long rsvd_56_63 : 8; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ADDR_MAP_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
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union uvh_si_addr_map_config_u {
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unsigned long v;
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struct uvh_si_addr_map_config_s {
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unsigned long m_skt : 6; /* RW */
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unsigned long rsvd_6_7: 2; /* */
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unsigned long n_skt : 4; /* RW */
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unsigned long rsvd_12_63: 52; /* */
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} s;
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};
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#endif /* __ASM_X86_UV_MMRS__ */
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