403 lines
11 KiB
C
403 lines
11 KiB
C
/*
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* setup.c
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*
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* BRIEF MODULE DESCRIPTION
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* Momentum Computer Ocelot-3 board dependent boot routines
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*
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* Copyright (C) 1996, 1997, 01, 05 Ralf Baechle
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* Copyright (C) 2000 RidgeRun, Inc.
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* Copyright (C) 2001 Red Hat, Inc.
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* Copyright (C) 2002 Momentum Computer
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*
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* Author: Matthew Dharm, Momentum Computer
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* mdharm@momenco.com
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*
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* Louis Hamilton, Red Hat, Inc.
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* hamilton@redhat.com [MIPS64 modifications]
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*
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* Copyright 2004 PMC-Sierra
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* Author: Manish Lachwani (lachwani@pmc-sierra.com)
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*
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* Copyright (C) 2004 MontaVista Software Inc.
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* Author: Manish Lachwani, mlachwani@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mc146818rtc.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/timex.h>
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#include <linux/bootmem.h>
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#include <linux/mv643xx.h>
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#include <linux/pm.h>
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#include <asm/time.h>
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#include <asm/page.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/reboot.h>
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#include <asm/mc146818rtc.h>
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#include <asm/tlbflush.h>
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#include "ocelot_3_fpga.h"
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/* Marvell Discovery Register Base */
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unsigned long marvell_base = (signed)0xf4000000;
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/* CPU clock */
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unsigned long cpu_clock;
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/* RTC/NVRAM */
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unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
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/* FPGA Base */
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unsigned long ocelot_fpga_base = (signed)0xfc000000;
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/* Serial base */
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unsigned long uart_base = (signed)0xfd000000;
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/*
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* Marvell Discovery SRAM. This is one place where Ethernet
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* Tx and Rx descriptors can be placed to improve performance
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*/
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extern unsigned long mv64340_sram_base;
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/* These functions are used for rebooting or halting the machine*/
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extern void momenco_ocelot_restart(char *command);
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extern void momenco_ocelot_halt(void);
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extern void momenco_ocelot_power_off(void);
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void momenco_time_init(void);
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static char reset_reason;
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void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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static inline unsigned long ENTRYLO(unsigned long paddr)
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{
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return ((paddr & PAGE_MASK) |
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(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
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_CACHE_UNCACHED)) >> 6;
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}
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void __init bus_error_init(void)
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{
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/* nothing */
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}
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/*
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* setup code for a handoff from a version 2 PMON 2000 PROM
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*/
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void setup_wired_tlb_entries(void)
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{
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write_c0_wired(0);
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local_flush_tlb_all();
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/* marvell and extra space */
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add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
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/* fpga, rtc, and uart */
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add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
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}
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#define CONV_BCD_TO_BIN(val) (((val) & 0xf) + (((val) >> 4) * 10))
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#define CONV_BIN_TO_BCD(val) (((val) % 10) + (((val) / 10) << 4))
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unsigned long m48t37y_get_time(void)
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{
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unsigned int year, month, day, hour, min, sec;
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unsigned long flags;
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spin_lock_irqsave(&rtc_lock, flags);
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/* stop the update */
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rtc_base[0x7ff8] = 0x40;
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year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
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year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
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month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
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day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
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hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
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min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
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sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
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/* start the update */
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rtc_base[0x7ff8] = 0x00;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return mktime(year, month, day, hour, min, sec);
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}
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int m48t37y_set_time(unsigned long sec)
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{
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struct rtc_time tm;
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unsigned long flags;
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/* convert to a more useful format -- note months count from 0 */
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to_tm(sec, &tm);
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tm.tm_mon += 1;
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spin_lock_irqsave(&rtc_lock, flags);
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/* enable writing */
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rtc_base[0x7ff8] = 0x80;
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/* year */
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rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
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rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
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/* month */
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rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
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/* day */
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rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
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/* hour/min/sec */
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rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
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rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
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rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
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/* day of week -- not really used, but let's keep it up-to-date */
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rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
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/* disable writing */
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rtc_base[0x7ff8] = 0x00;
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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void momenco_timer_setup(struct irqaction *irq)
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{
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setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */
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}
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void momenco_time_init(void)
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{
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setup_wired_tlb_entries();
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/*
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* Ocelot-3 board has been built with both
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* the Rm7900 and the Rm7065C
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*/
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mips_hpt_frequency = cpu_clock / 2;
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board_timer_setup = momenco_timer_setup;
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rtc_get_time = m48t37y_get_time;
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rtc_set_time = m48t37y_set_time;
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}
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/*
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* PCI Support for Ocelot-3
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*/
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/* Bus #0 IO and MEM space */
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#define OCELOT_3_PCI_IO_0_START 0xe0000000
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#define OCELOT_3_PCI_IO_0_SIZE 0x08000000
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#define OCELOT_3_PCI_MEM_0_START 0xc0000000
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#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000
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/* Bus #1 IO and MEM space */
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#define OCELOT_3_PCI_IO_1_START 0xe8000000
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#define OCELOT_3_PCI_IO_1_SIZE 0x08000000
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#define OCELOT_3_PCI_MEM_1_START 0xd0000000
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#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000
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static struct resource mv_pci_io_mem0_resource = {
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.name = "MV64340 PCI0 IO MEM",
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.start = OCELOT_3_PCI_IO_0_START,
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.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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static struct resource mv_pci_io_mem1_resource = {
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.name = "MV64340 PCI1 IO MEM",
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.start = OCELOT_3_PCI_IO_1_START,
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.end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
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.flags = IORESOURCE_IO,
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};
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static struct resource mv_pci_mem0_resource = {
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.name = "MV64340 PCI0 MEM",
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.start = OCELOT_3_PCI_MEM_0_START,
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.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource mv_pci_mem1_resource = {
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.name = "MV64340 PCI1 MEM",
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.start = OCELOT_3_PCI_MEM_1_START,
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.end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct mv_pci_controller mv_bus0_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = &mv_pci_mem0_resource,
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.io_resource = &mv_pci_io_mem0_resource,
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},
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.config_addr = MV64340_PCI_0_CONFIG_ADDR,
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.config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
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};
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static struct mv_pci_controller mv_bus1_controller = {
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.pcic = {
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.pci_ops = &mv_pci_ops,
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.mem_resource = &mv_pci_mem1_resource,
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.io_resource = &mv_pci_io_mem1_resource,
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},
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.config_addr = MV64340_PCI_1_CONFIG_ADDR,
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.config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
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};
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static __init int __init ja_pci_init(void)
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{
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uint32_t enable;
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extern int pci_probe_only;
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/* PMON will assign PCI resources */
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pci_probe_only = 1;
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enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
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/*
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* We require at least one enabled I/O or PCI memory window or we
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* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
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*/
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if (enable & (0x01 << 9) || enable & (0x01 << 10))
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register_pci_controller(&mv_bus0_controller.pcic);
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if (enable & (0x01 << 14) || enable & (0x01 << 15))
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register_pci_controller(&mv_bus1_controller.pcic);
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ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
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OCELOT_3_PCI_IO_1_SIZE - 1;
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iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
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OCELOT_3_PCI_MEM_1_SIZE - 1;
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set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
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return 0;
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}
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arch_initcall(ja_pci_init);
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void __init plat_setup(void)
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{
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unsigned int tmpword;
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board_time_init = momenco_time_init;
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_machine_restart = momenco_ocelot_restart;
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_machine_halt = momenco_ocelot_halt;
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pm_power_off = momenco_ocelot_power_off;
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/* Wired TLB entries */
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setup_wired_tlb_entries();
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/* shut down ethernet ports, just to be sure our memory doesn't get
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* corrupted by random ethernet traffic.
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*/
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MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
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MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
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MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
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MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
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do {}
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while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
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do {}
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while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
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do {}
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while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
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do {}
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while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
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MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
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MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
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MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
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MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
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/* Turn off the Bit-Error LED */
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OCELOT_FPGA_WRITE(0x80, CLR);
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tmpword = OCELOT_FPGA_READ(BOARDREV);
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if (tmpword < 26)
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printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
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'A'+tmpword);
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else
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printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
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tmpword);
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tmpword = OCELOT_FPGA_READ(FPGA_REV);
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printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
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tmpword = OCELOT_FPGA_READ(RESET_STATUS);
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printk("Reset reason: 0x%x\n", tmpword);
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switch (tmpword) {
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case 0x1:
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printk(" - Power-up reset\n");
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break;
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case 0x2:
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printk(" - Push-button reset\n");
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break;
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case 0x4:
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printk(" - cPCI bus reset\n");
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break;
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case 0x8:
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printk(" - Watchdog reset\n");
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break;
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case 0x10:
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printk(" - Software reset\n");
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break;
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default:
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printk(" - Unknown reset cause\n");
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}
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reset_reason = tmpword;
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OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
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tmpword = OCELOT_FPGA_READ(CPCI_ID);
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printk("cPCI ID register: 0x%02x\n", tmpword);
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printk(" - Slot number: %d\n", tmpword & 0x1f);
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printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
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printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
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tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
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printk("Board Status register: 0x%02x\n", tmpword);
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printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
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printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
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printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
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/* Support for 128 MB memory */
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add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
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}
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