2326e2b999
Disable Bus Master, SERR# and INTx to ensure that no new Requests will be generated from the device before turning power off, in accordance with the specification. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
295 lines
8.3 KiB
C
295 lines
8.3 KiB
C
/*
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* PCI Express Hot Plug Controller Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include "../pci.h"
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#include "pciehp.h"
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static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
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{
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u16 pci_cmd, pci_bctl;
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if (hpp->revision > 1) {
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printk(KERN_WARNING "%s: Rev.%d type0 record not supported\n",
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__FUNCTION__, hpp->revision);
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return;
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}
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
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pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
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if (hpp->enable_serr)
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pci_cmd |= PCI_COMMAND_SERR;
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else
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pci_cmd &= ~PCI_COMMAND_SERR;
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if (hpp->enable_perr)
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pci_cmd |= PCI_COMMAND_PARITY;
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else
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pci_cmd &= ~PCI_COMMAND_PARITY;
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pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
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/* Program bridge control value */
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
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hpp->latency_timer);
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
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if (hpp->enable_serr)
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pci_bctl |= PCI_BRIDGE_CTL_SERR;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_SERR;
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if (hpp->enable_perr)
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pci_bctl |= PCI_BRIDGE_CTL_PARITY;
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else
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pci_bctl &= ~PCI_BRIDGE_CTL_PARITY;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
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}
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}
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static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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{
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int pos;
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u16 reg16;
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u32 reg32;
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if (hpp->revision > 1) {
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printk(KERN_WARNING "%s: Rev.%d type2 record not supported\n",
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__FUNCTION__, hpp->revision);
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return;
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}
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/* Find PCI Express capability */
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pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (!pos)
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return;
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/* Initialize Device Control Register */
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16);
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reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or;
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
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/* Initialize Link Control Register */
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if (dev->subordinate) {
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pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, ®16);
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reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
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| hpp->pci_exp_lnkctl_or;
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pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
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}
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/* Find Advanced Error Reporting Enhanced Capability */
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (!pos)
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return;
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/* Initialize Uncorrectable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
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reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
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/* Initialize Uncorrectable Error Severity Register */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
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reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
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/* Initialize Correctable Error Mask Register */
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pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
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reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
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/* Initialize Advanced Error Capabilities and Control Register */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
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reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
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/*
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* FIXME: The following two registers are not supported yet.
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*
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* o Secondary Uncorrectable Error Severity Register
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* o Secondary Uncorrectable Error Mask Register
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*/
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}
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static void program_fw_provided_values(struct pci_dev *dev)
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{
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struct pci_dev *cdev;
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struct hotplug_params hpp;
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/* Program hpp values for this device */
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if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
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(dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
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return;
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if (pciehp_get_hp_params_from_firmware(dev, &hpp)) {
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printk(KERN_WARNING "%s: Could not get hotplug parameters\n",
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__FUNCTION__);
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return;
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}
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if (hpp.t2)
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program_hpp_type2(dev, hpp.t2);
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if (hpp.t0)
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program_hpp_type0(dev, hpp.t0);
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/* Program child devices */
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if (dev->subordinate) {
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list_for_each_entry(cdev, &dev->subordinate->devices,
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bus_list)
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program_fw_provided_values(cdev);
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}
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}
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static int pciehp_add_bridge(struct pci_dev *dev)
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{
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struct pci_bus *parent = dev->bus;
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int pass, busnr, start = parent->secondary;
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int end = parent->subordinate;
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for (busnr = start; busnr <= end; busnr++) {
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if (!pci_find_bus(pci_domain_nr(parent), busnr))
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break;
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}
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if (busnr-- > end) {
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err("No bus number available for hot-added bridge %s\n",
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pci_name(dev));
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return -1;
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}
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for (pass = 0; pass < 2; pass++)
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busnr = pci_scan_bridge(parent, dev, busnr, pass);
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if (!dev->subordinate)
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return -1;
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pci_bus_size_bridges(dev->subordinate);
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pci_bus_assign_resources(parent);
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pci_enable_bridges(parent);
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pci_bus_add_devices(parent);
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return 0;
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}
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int pciehp_configure_device(struct slot *p_slot)
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{
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struct pci_dev *dev;
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struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
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int num, fn;
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dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
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if (dev) {
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err("Device %s already exists at %x:%x, cannot hot-add\n",
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pci_name(dev), p_slot->bus, p_slot->device);
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pci_dev_put(dev);
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return -EINVAL;
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}
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num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0));
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if (num == 0) {
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err("No new device found\n");
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return -ENODEV;
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}
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for (fn = 0; fn < 8; fn++) {
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dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn));
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if (!dev)
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continue;
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if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
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err("Cannot hot-add display device %s\n",
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pci_name(dev));
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pci_dev_put(dev);
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continue;
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}
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if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
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(dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) {
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pciehp_add_bridge(dev);
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}
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program_fw_provided_values(dev);
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pci_dev_put(dev);
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}
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pci_bus_assign_resources(parent);
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pci_bus_add_devices(parent);
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return 0;
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}
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int pciehp_unconfigure_device(struct slot *p_slot)
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{
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int ret, rc = 0;
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int j;
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u8 bctl = 0;
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u8 presence = 0;
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struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
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u16 command;
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dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus,
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p_slot->device);
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ret = p_slot->hpc_ops->get_adapter_status(p_slot, &presence);
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if (ret)
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presence = 0;
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for (j = 0; j < 8; j++) {
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struct pci_dev* temp = pci_get_slot(parent,
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(p_slot->device << 3) | j);
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if (!temp)
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continue;
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if ((temp->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
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err("Cannot remove display device %s\n",
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pci_name(temp));
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pci_dev_put(temp);
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continue;
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}
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if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) {
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pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, &bctl);
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if (bctl & PCI_BRIDGE_CTL_VGA) {
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err("Cannot remove display device %s\n",
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pci_name(temp));
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pci_dev_put(temp);
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continue;
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}
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}
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pci_remove_bus_device(temp);
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/*
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* Ensure that no new Requests will be generated from
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* the device.
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*/
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if (presence) {
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pci_read_config_word(temp, PCI_COMMAND, &command);
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command &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
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command |= PCI_COMMAND_INTX_DISABLE;
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pci_write_config_word(temp, PCI_COMMAND, command);
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}
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pci_dev_put(temp);
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}
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/*
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* Some PCI Express root ports require fixup after hot-plug operation.
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*/
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if (pcie_mch_quirk)
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pci_fixup_device(pci_fixup_final, p_slot->ctrl->pci_dev);
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return rc;
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}
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