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Merge branch 'feat-fst280' of bitbucket.org:k1jt/wsjtx into feat-fst280
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commit
bf51dfd61d
@ -51,7 +51,7 @@ program fst240sim
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if(nsec.eq.30) nsps=1680
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if(nsec.eq.60) nsps=3888
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if(nsec.eq.120) nsps=8200
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if(nsec.eq.300) nsps=21168
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if(nsec.eq.300) nsps=21504
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if(nsps.eq.0) then
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print*,'Invalid TR sequence length.'
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go to 999
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@ -376,7 +376,7 @@ write(21,'(8i4,f7.1,f7.2,3f7.1,1x,a37)') &
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integer hmod,isyncword(0:7)
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real f0save
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data isyncword/0,1,3,2,1,0,2,3/
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data first/.true./,f0save/0.0/,nss0/-1/
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data first/.true./,f0save/-99.9/,nss0/-1/
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save first,twopi,dt,fac,f0save,nss0
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p(z1)=(real(z1*fac)**2 + aimag(z1*fac)**2)**0.5 !Compute power
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@ -444,7 +444,6 @@ write(21,'(8i4,f7.1,f7.2,3f7.1,1x,a37)') &
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s4=s4+abs(z4)/(8*nss)
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s5=s5+abs(z5)/(8*nss)
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enddo
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sync = s1+s2+s3+s4+s5
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return
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