<p>OPENSSL_ia32cap - the x86[_64] processor capabilities vector</p>
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<h1><aname="synopsis">SYNOPSIS</a></h1>
<pre>
env OPENSSL_ia32cap=... <application></pre>
<p>
</p>
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<h1><aname="description">DESCRIPTION</a></h1>
<p>OpenSSL supports a range of x86[_64] instruction set extensions. These
extensions are denoted by individual bits in capability vector returned
by processor in EDX:ECX register pair after executing CPUID instruction
with EAX=1 input value (see Intel Application Note #241618). This vector
is copied to memory upon toolkit initialization and used to choose
between different code paths to provide optimal performance across wide
range of processors. For the moment of this writing following bits are
significant:</p>
<dl>
<dt><strong><aname="bit_4_denoting_presence_of_time_stamp_counter"class="item">bit #4 denoting presence of Time-Stamp Counter.</a></strong></dt>
<dt><strong><aname="bit_19_denoting_availability_of_clflush_instruction"class="item">bit #19 denoting availability of CLFLUSH instruction;</a></strong></dt>
<dt><strong><aname="bit_20_reserved_by_intel_is_used_to_choose_among_rc4_code_paths"class="item">bit #20, reserved by Intel, is used to choose among RC4 code paths;</a></strong></dt>
<dt><strong><aname="bit_28_denoting_hyperthreading_which_is_used_to_distinguish_cores_with_shared_cache"class="item">bit #28 denoting Hyperthreading, which is used to distinguish
cores with shared cache;</a></strong></dt>
<dt><strong><aname="bit_30_reserved_by_intel_denotes_specifically_intel_cpus"class="item">bit #30, reserved by Intel, denotes specifically Intel CPUs;</a></strong></dt>
<dt><strong><aname="bit_33_denoting_availability_of_pclmulqdq_instruction"class="item">bit #33 denoting availability of PCLMULQDQ instruction;</a></strong></dt>
<dt><strong><aname="support"class="item">bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);</a></strong></dt>
<dt><strong><aname="bit_54_denoting_availability_of_movbe_instruction"class="item">bit #54 denoting availability of MOVBE instruction;</a></strong></dt>
<dt><strong><aname="bit_57_denoting_aes_ni_instruction_set_extension"class="item">bit #57 denoting AES-NI instruction set extension;</a></strong></dt>
<dt><strong><aname="bit_58_xsave_bit_lack_of_which_in_combination_with_movbe_is_used_to_identify_atom_silvermont_core"class="item">bit #58, XSAVE bit, lack of which in combination with MOVBE is used
to identify Atom Silvermont core;</a></strong></dt>
<dt><strong><aname="bit_59_osxsave_bit_denoting_availability_of_ymm_registers"class="item">bit #59, OSXSAVE bit, denoting availability of YMM registers;</a></strong></dt>
effect. Alternatively you can reconfigure the toolkit with no-sse2
option and recompile.</p>
<p>Less intuitive is clearing bit #28, or ~0x10000000 in the "environment
variable" terms. The truth is that it's not copied from CPUID output
verbatim, but is adjusted to reflect whether or not the data cache is
actually shared between logical cores. This in turn affects the decision
on whether or not expensive countermeasures against cache-timing attacks
are applied, most notably in AES assembler module.</p>
<p>The capability vector is further extended with EBX value returned by
CPUID with EAX=7 and ECX=0 as input. Following bits are significant:</p>
<dl>
<dt><strong><aname="bit_64_3_denoting_availability_of_bmi1_instructions_e_g_andn"class="item">bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;</a></strong></dt>
<dt><strong><aname="bit_64_5_denoting_availability_of_avx2_instructions"class="item">bit #64+5 denoting availability of AVX2 instructions;</a></strong></dt>
<dt><strong><aname="bit_64_8_denoting_availability_of_bmi2_instructions_e_g_mulx_and_rorx"class="item">bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
and RORX;</a></strong></dt>
<dt><strong><aname="bit_64_16_denoting_availability_of_avx512f_extension"class="item">bit #64+16 denoting availability of AVX512F extension;</a></strong></dt>
<dt><strong><aname="bit_64_18_denoting_availability_of_rdseed_instruction"class="item">bit #64+18 denoting availability of RDSEED instruction;</a></strong></dt>
<dt><strong><aname="bit_64_19_denoting_availability_of_adcx_and_adox_instructions"class="item">bit #64+19 denoting availability of ADCX and ADOX instructions;</a></strong></dt>
<dt><strong><aname="bit_64_21_denoting_availability_of_vpmadd52_lh_uq_instructions_a_k_a_avx512ifma_extension"class="item">bit #64+21 denoting availability of VPMADD52[LH]UQ instructions,
a.k.a. AVX512IFMA extension;</a></strong></dt>
<dt><strong><aname="bit_64_29_denoting_availability_of_sha_extension"class="item">bit #64+29 denoting availability of SHA extension;</a></strong></dt>
<dt><strong><aname="bit_64_30_denoting_availability_of_avx512bw_extension"class="item">bit #64+30 denoting availability of AVX512BW extension;</a></strong></dt>
<dt><strong><aname="bit_64_31_denoting_availability_of_avx512vl_extension"class="item">bit #64+31 denoting availability of AVX512VL extension;</a></strong></dt>
<dt><strong><aname="bit_64_41_denoting_availability_of_vaes_extension"class="item">bit #64+41 denoting availability of VAES extension;</a></strong></dt>
<dt><strong><aname="bit_64_42_denoting_availability_of_vpclmulqdq_extension"class="item">bit #64+42 denoting availability of VPCLMULQDQ extension;</a></strong></dt>