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https://github.com/f4exb/sdrangel.git
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Added a frequency lock loop
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f4exb
parent
c495f82235
commit
d29958d51f
@ -34,6 +34,7 @@ set(sdrbase_SOURCES
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dsp/filterrc.cpp
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dsp/filtermbe.cpp
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dsp/filerecord.cpp
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dsp/freqlockcomplex.cpp
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dsp/interpolator.cpp
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dsp/hbfiltertraits.cpp
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dsp/lowpass.cpp
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@ -124,6 +125,7 @@ set(sdrbase_HEADERS
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dsp/filterrc.h
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dsp/filtermbe.h
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dsp/filerecord.h
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dsp/freqlockcomplex.h
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dsp/gfft.h
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dsp/iirfilter.h
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dsp/interpolator.h
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@ -271,6 +273,7 @@ include_directories(
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.
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${CMAKE_SOURCE_DIR}/exports
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${CMAKE_SOURCE_DIR}/httpserver
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${CMAKE_SOURCE_DIR}/kitiirfir
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${CMAKE_SOURCE_DIR}/qrtplib
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${CMAKE_SOURCE_DIR}/swagger/sdrangel/code/qt5/client
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)
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@ -278,6 +281,7 @@ include_directories(
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target_link_libraries(sdrbase
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${QT_LIBRARIES}
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httpserver
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kitiirfir
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qrtplib
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swagger
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)
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122
sdrbase/dsp/freqlockcomplex.cpp
Normal file
122
sdrbase/dsp/freqlockcomplex.cpp
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@ -0,0 +1,122 @@
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///////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2018 F4EXB //
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// written by Edouard Griffiths //
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// //
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// See: http://liquidsdr.org/blog/pll-howto/ //
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// Fixed filter registers saturation //
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// Added order for PSK locking. This brilliant idea actually comes from this //
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// post: https://www.dsprelated.com/showthread/comp.dsp/36356-1.php //
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// //
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// This program is free software; you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation as version 3 of the License, or //
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// //
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// This program is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY; without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License V3 for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with this program. If not, see <http://www.gnu.org/licenses/>. //
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///////////////////////////////////////////////////////////////////////////////////
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#include "freqlockcomplex.h"
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#include "IIRFilterCode.h"
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FreqLockComplex::FreqLockComplex() :
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m_a0(1.0),
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m_a1(1.0),
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m_a2(1.0),
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m_b0(1.0),
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m_b1(1.0),
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m_b2(1.0),
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m_v0(0.0),
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m_v1(0.0),
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m_v2(0.0),
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m_y(1.0, 0.0),
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m_prod(1.0, 0.0),
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m_yRe(1.0),
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m_yIm(0.0),
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m_freq(0.0),
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m_phi(0.0),
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m_iir(0)
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{
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}
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FreqLockComplex::~FreqLockComplex()
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{
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if (m_iir) {
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delete m_iir;
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}
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}
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void FreqLockComplex::reset()
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{
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m_v0 = 0.0f;
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m_v1 = 0.0f;
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m_v2 = 0.0f;
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m_y.real(1.0);
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m_y.imag(0.0);
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m_prod.real(1.0);
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m_prod.imag(0.0);
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m_yRe = 1.0f;
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m_yIm = 0.0f;
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m_freq = 0.0f;
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m_phi = 0.0f;
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}
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// wn is in terms of Nyquist. For example, if the sampling frequency = 20 kHz
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// and the 3 dB corner frequency is 1.5 kHz, then OmegaC = 0.15
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// i.e. 100.0 / (SR/2) or 200 / SR for 100 Hz
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void FreqLockComplex::computeCoefficients(float wn)
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{
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kitiirfir::TIIRFilterParams params;
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params.BW = 0.0; // For band pass and notch filters - unused here
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params.Gamma = 0.0; // For Adjustable Gauss. - unused here
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params.IIRPassType = kitiirfir::iirLPF;
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params.NumPoles = 1;
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params.OmegaC = wn;
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params.ProtoType = kitiirfir::BUTTERWORTH;
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params.Ripple = 0.0; // For Elliptic and Chebyshev - unused here
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params.StopBanddB = 0.0; // For Elliptic and Inverse Chebyshev - unused here
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params.dBGain = 0.0;
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kitiirfir::TIIRCoeff coeff = kitiirfir::CalcIIRFilterCoeff(params);
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float a[3], b[3];
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a[0] = coeff.a0[0];
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a[1] = coeff.a1[0];
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a[2] = coeff.a2[0];
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b[0] = coeff.b0[0];
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b[1] = coeff.b1[0];
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b[2] = coeff.b2[0];
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qDebug("FreqLockComplex::computeCoefficients: b: %f %f %f", b[0], b[1], b[2]);
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qDebug("FreqLockComplex::computeCoefficients: a: %f %f %f", a[0], a[1], a[2]);
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m_iir = new IIRFilter<float, 2>(a, b);
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}
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void FreqLockComplex::feed(float re, float im)
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{
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m_yRe = cos(m_phi);
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m_yIm = sin(m_phi);
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std::complex<float> y(m_yRe, m_yIm);
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std::complex<float> x(re, im);
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std::complex<float> prod = x * m_y;
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// Discriminator: cross * sign(dot) / dt
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float cross = m_prod.real()*prod.imag() - prod.real()*m_prod.imag();
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float dot = m_prod.real()*prod.real() + m_prod.imag()*prod.imag();
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float eF = cross * (dot < 0 ? -1 : 1); // frequency error
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// LPF section
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float efHat = m_iir->run(eF);
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m_freq = efHat; // correct instantaneous frequency
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m_phi += efHat; // advance phase with instantaneous frequency
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m_prod = prod; // store previous product
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}
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62
sdrbase/dsp/freqlockcomplex.h
Normal file
62
sdrbase/dsp/freqlockcomplex.h
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@ -0,0 +1,62 @@
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///////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2018 F4EXB //
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// written by Edouard Griffiths //
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// //
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// See: http://liquidsdr.org/blog/pll-howto/ //
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// Fixed filter registers saturation //
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// Added order for PSK locking. This brilliant idea actually comes from this //
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// post: https://www.dsprelated.com/showthread/comp.dsp/36356-1.php //
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// //
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// This program is free software; you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation as version 3 of the License, or //
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// //
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// This program is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY; without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License V3 for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with this program. If not, see <http://www.gnu.org/licenses/>. //
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///////////////////////////////////////////////////////////////////////////////////
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#ifndef SDRBASE_DSP_FREQLOCKCOMPLEX_H_
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#define SDRBASE_DSP_FREQLOCKCOMPLEX_H_
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#include "dsp/dsptypes.h"
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#include "iirfilter.h"
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#include "export.h"
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/** General purpose Phase-locked loop using complex analytic signal input. */
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class SDRBASE_API FreqLockComplex
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{
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public:
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FreqLockComplex();
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~FreqLockComplex();
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void reset();
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void computeCoefficients(float wn);
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/** Feed PLL with a new signa sample */
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void feed(float re, float im);
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private:
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float m_a0;
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float m_a1;
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float m_a2;
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float m_b0;
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float m_b1;
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float m_b2;
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float m_v0;
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float m_v1;
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float m_v2;
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std::complex<float> m_y;
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std::complex<float> m_prod;
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float m_yRe;
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float m_yIm;
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float m_freq;
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float m_phi;
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IIRFilter<float, 2> *m_iir;
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};
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#endif /* SDRBASE_DSP_FREQLOCKCOMPLEX_H_ */
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